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[src/trunk]: src/sys/arch/sgimips/hpc KNF and misc cosmetics.
details: https://anonhg.NetBSD.org/src/rev/24fcbe102105
branches: trunk
changeset: 761365:24fcbe102105
user: tsutsui <tsutsui%NetBSD.org@localhost>
date: Tue Jan 25 13:12:39 2011 +0000
description:
KNF and misc cosmetics.
diffstat:
sys/arch/sgimips/hpc/if_sq.c | 307 +++++++++++++++++++++---------------------
sys/arch/sgimips/hpc/sqvar.h | 41 ++--
2 files changed, 173 insertions(+), 175 deletions(-)
diffs (truncated from 845 to 300 lines):
diff -r 63470c87e825 -r 24fcbe102105 sys/arch/sgimips/hpc/if_sq.c
--- a/sys/arch/sgimips/hpc/if_sq.c Tue Jan 25 12:56:57 2011 +0000
+++ b/sys/arch/sgimips/hpc/if_sq.c Tue Jan 25 13:12:39 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_sq.c,v 1.39 2011/01/25 12:43:30 tsutsui Exp $ */
+/* $NetBSD: if_sq.c,v 1.40 2011/01/25 13:12:39 tsutsui Exp $ */
/*
* Copyright (c) 2001 Rafal K. Boni
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.39 2011/01/25 12:43:30 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.40 2011/01/25 13:12:39 tsutsui Exp $");
#include <sys/param.h>
@@ -114,14 +114,14 @@
static void sq_txring_hpc1(struct sq_softc *);
static void sq_txring_hpc3(struct sq_softc *);
static void sq_reset(struct sq_softc *);
-static int sq_add_rxbuf(struct sq_softc *, int);
-static void sq_dump_buffer(paddr_t addr, psize_t len);
+static int sq_add_rxbuf(struct sq_softc *, int);
+static void sq_dump_buffer(paddr_t addr, psize_t len);
static void sq_trace_dump(struct sq_softc *);
CFATTACH_DECL_NEW(sq, sizeof(struct sq_softc),
sq_match, sq_attach, NULL, NULL);
-#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
+#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
#define sq_seeq_read(sc, off) \
bus_space_read_1(sc->sc_regt, sc->sc_regh, off)
@@ -129,9 +129,9 @@
bus_space_write_1(sc->sc_regt, sc->sc_regh, off, val)
#define sq_hpc_read(sc, off) \
- bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off)
+ bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off)
#define sq_hpc_write(sc, off, val) \
- bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val)
+ bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val)
/* MAC address offset for non-onboard implementations */
#define SQ_HPC_EEPROM_ENADDR 250
@@ -154,20 +154,20 @@
ha->ha_devoff + (SEEQ_TXSTAT << 2));
if (platform.badaddr((void *)reset, sizeof(reset)))
- return (0);
+ return 0;
*(volatile uint32_t *)reset = 0x1;
delay(20);
*(volatile uint32_t *)reset = 0x0;
if (platform.badaddr((void *)txstat, sizeof(txstat)))
- return (0);
+ return 0;
if ((*(volatile uint32_t *)txstat & 0xff) == TXSTAT_OLDNEW)
- return (1);
+ return 1;
}
- return (0);
+ return 0;
}
static void
@@ -184,18 +184,16 @@
sc->hpc_regs = haa->hpc_regs; /* HPC register definitions */
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
- haa->ha_dmaoff,
- sc->hpc_regs->enet_regs_size,
- &sc->sc_hpch)) != 0) {
+ haa->ha_dmaoff, sc->hpc_regs->enet_regs_size,
+ &sc->sc_hpch)) != 0) {
printf(": unable to map HPC DMA registers, error = %d\n", err);
goto fail_0;
}
sc->sc_regt = haa->ha_st;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
- haa->ha_devoff,
- sc->hpc_regs->enet_devregs_size,
- &sc->sc_regh)) != 0) {
+ haa->ha_devoff, sc->hpc_regs->enet_devregs_size,
+ &sc->sc_regh)) != 0) {
printf(": unable to map Seeq registers, error = %d\n", err);
goto fail_0;
}
@@ -203,33 +201,32 @@
sc->sc_dmat = haa->ha_dmat;
if ((err = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control),
- PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg,
- 1, &sc->sc_ncdseg, BUS_DMA_NOWAIT)) != 0) {
+ PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg, 1, &sc->sc_ncdseg,
+ BUS_DMA_NOWAIT)) != 0) {
printf(": unable to allocate control data, error = %d\n", err);
goto fail_0;
}
if ((err = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg,
- sizeof(struct sq_control),
- (void **)&sc->sc_control,
- BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
+ sizeof(struct sq_control), (void **)&sc->sc_control,
+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
printf(": unable to map control data, error = %d\n", err);
goto fail_1;
}
- if ((err = bus_dmamap_create(sc->sc_dmat, sizeof(struct sq_control),
- 1, sizeof(struct sq_control), PAGE_SIZE,
- BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) {
+ if ((err = bus_dmamap_create(sc->sc_dmat,
+ sizeof(struct sq_control), 1, sizeof(struct sq_control), PAGE_SIZE,
+ BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) {
printf(": unable to create DMA map for control data, error "
- "= %d\n", err);
+ "= %d\n", err);
goto fail_2;
}
- if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap, sc->sc_control,
- sizeof(struct sq_control),
- NULL, BUS_DMA_NOWAIT)) != 0) {
+ if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap,
+ sc->sc_control, sizeof(struct sq_control), NULL,
+ BUS_DMA_NOWAIT)) != 0) {
printf(": unable to load DMA map for control data, error "
- "= %d\n", err);
+ "= %d\n", err);
goto fail_3;
}
@@ -237,31 +234,31 @@
/* Create transmit buffer DMA maps */
for (i = 0; i < SQ_NTXDESC; i++) {
- if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
- 0, BUS_DMA_NOWAIT,
- &sc->sc_txmap[i])) != 0) {
- printf(": unable to create tx DMA map %d, error = %d\n",
- i, err);
- goto fail_4;
- }
+ if ((err = bus_dmamap_create(sc->sc_dmat,
+ MCLBYTES, 1, MCLBYTES, 0,
+ BUS_DMA_NOWAIT, &sc->sc_txmap[i])) != 0) {
+ printf(": unable to create tx DMA map %d, error = %d\n",
+ i, err);
+ goto fail_4;
+ }
}
/* Create receive buffer DMA maps */
for (i = 0; i < SQ_NRXDESC; i++) {
- if ((err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
- 0, BUS_DMA_NOWAIT,
- &sc->sc_rxmap[i])) != 0) {
- printf(": unable to create rx DMA map %d, error = %d\n",
- i, err);
- goto fail_5;
- }
+ if ((err = bus_dmamap_create(sc->sc_dmat,
+ MCLBYTES, 1, MCLBYTES, 0,
+ BUS_DMA_NOWAIT, &sc->sc_rxmap[i])) != 0) {
+ printf(": unable to create rx DMA map %d, error = %d\n",
+ i, err);
+ goto fail_5;
+ }
}
/* Pre-allocate the receive buffers. */
for (i = 0; i < SQ_NRXDESC; i++) {
if ((err = sq_add_rxbuf(sc, i)) != 0) {
printf(": unable to allocate or map rx buffer %d\n,"
- " error = %d\n", i, err);
+ " error = %d\n", i, err);
goto fail_6;
}
}
@@ -274,7 +271,8 @@
* be true of the onboard HPC3 on IP22, since there is no eeprom,
* but rather the DS1386 RTC's battery-backed ram is used.
*/
- if (sc->sc_enaddr[0] != SGI_OUI_0 || sc->sc_enaddr[1] != SGI_OUI_1 ||
+ if (sc->sc_enaddr[0] != SGI_OUI_0 ||
+ sc->sc_enaddr[1] != SGI_OUI_1 ||
sc->sc_enaddr[2] != SGI_OUI_2) {
macaddr = ARCBIOS->GetEnvironmentVariable("eaddr");
if (macaddr == NULL) {
@@ -336,32 +334,32 @@
* Free any resources we've allocated during the failed attach
* attempt. Do this in reverse order and fall through.
*/
-fail_6:
+ fail_6:
for (i = 0; i < SQ_NRXDESC; i++) {
if (sc->sc_rxmbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]);
m_freem(sc->sc_rxmbuf[i]);
}
}
-fail_5:
+ fail_5:
for (i = 0; i < SQ_NRXDESC; i++) {
- if (sc->sc_rxmap[i] != NULL)
- bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]);
+ if (sc->sc_rxmap[i] != NULL)
+ bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]);
}
-fail_4:
+ fail_4:
for (i = 0; i < SQ_NTXDESC; i++) {
- if (sc->sc_txmap[i] != NULL)
- bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]);
+ if (sc->sc_txmap[i] != NULL)
+ bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]);
}
bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap);
-fail_3:
+ fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap);
-fail_2:
- bus_dmamem_unmap(sc->sc_dmat, (void *) sc->sc_control,
- sizeof(struct sq_control));
-fail_1:
+ fail_2:
+ bus_dmamem_unmap(sc->sc_dmat,
+ (void *)sc->sc_control, sizeof(struct sq_control));
+ fail_1:
bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg);
-fail_0:
+ fail_0:
return;
}
@@ -389,11 +387,12 @@
for (i = 0; i < ETHER_ADDR_LEN; i++)
sq_seeq_write(sc, i, sc->sc_enaddr[i]);
- sc->sc_rxcmd = RXCMD_IE_CRC |
- RXCMD_IE_DRIB |
- RXCMD_IE_SHORT |
- RXCMD_IE_END |
- RXCMD_IE_GOOD;
+ sc->sc_rxcmd =
+ RXCMD_IE_CRC |
+ RXCMD_IE_DRIB |
+ RXCMD_IE_SHORT |
+ RXCMD_IE_END |
+ RXCMD_IE_GOOD;
/*
* Set the receive filter -- this will add some bits to the
@@ -404,10 +403,11 @@
sq_set_filter(sc);
/* Set up Seeq transmit command register */
- sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_IE_UFLOW |
- TXCMD_IE_COLL |
- TXCMD_IE_16COLL |
- TXCMD_IE_GOOD);
+ sq_seeq_write(sc, SEEQ_TXCMD,
+ TXCMD_IE_UFLOW |
+ TXCMD_IE_COLL |
+ TXCMD_IE_16COLL |
+ TXCMD_IE_GOOD);
/* Now write the receive command register. */
sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd);
@@ -416,23 +416,25 @@
* Set up HPC ethernet PIO and DMA configurations.
*
* The PROM appears to do most of this for the onboard HPC3, but
- * not for the Challenge S's IOPLUS chip. We copy how the onboard
+ * not for the Challenge S's IOPLUS chip. We copy how the onboard
* chip is configured and assume that it's correct for both.
*/
if (sc->hpc_regs->revision == 3) {
uint32_t dmareg, pioreg;
- pioreg = HPC3_ENETR_PIOCFG_P1(1) |
- HPC3_ENETR_PIOCFG_P2(6) |
- HPC3_ENETR_PIOCFG_P3(1);
+ pioreg =
+ HPC3_ENETR_PIOCFG_P1(1) |
+ HPC3_ENETR_PIOCFG_P2(6) |
+ HPC3_ENETR_PIOCFG_P3(1);
- dmareg = HPC3_ENETR_DMACFG_D1(6) |
- HPC3_ENETR_DMACFG_D2(2) |
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