[src/trunk]: src/sys/arch/mips/mips Restore (and update) half of the TLB miss...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2d334fa5ffcd
branches:  trunk
changeset: 755806:2d334fa5ffcd
user:      simonb <simonb%NetBSD.org@localhost>
date:      Tue Jun 22 12:42:21 2010 +0000

description:
Restore (and update) half of the TLB miss handler that went missing
during the mips64 merge.  This gets my sbmips kernel booting to the
login prompt.  This code could not possibly have been tested after
the merge.

Should fix PR port-mips/43431.

diffstat:

 sys/arch/mips/mips/mipsX_subr.S |  13 ++++++++++---
 1 files changed, 10 insertions(+), 3 deletions(-)

diffs (32 lines):

diff -r b44f58e27bc1 -r 2d334fa5ffcd sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S   Tue Jun 22 12:33:15 2010 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S   Tue Jun 22 12:42:21 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mipsX_subr.S,v 1.35 2009/12/14 00:46:06 matt Exp $     */
+/*     $NetBSD: mipsX_subr.S,v 1.36 2010/06/22 12:42:21 simonb Exp $   */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -342,13 +342,20 @@
        _MFC0   k0, MIPS_COP_0_BAD_VADDR        #00: k0=bad address
        lui     k1, %hi(segbase)                #01: k1=hi of segbase
        bltz    k0, 4f                          #02: k0<0 -> 4f (kernel fault)
-       PTR_SRL k0, (2*PGSHIFT-2-PTR_SCALESHIFT)#03: k0=seg offset (almost)
+       PTR_SRL k0, 2*PGSHIFT-2-PTR_SCALESHIFT  #03: k0=seg offset (almost)
        PTR_L   k1, %lo(segbase)(k1)            #04: k1=segment tab base
-       andi    k0, k0, (NBPG-(1<<PTR_SCALESHIFT))#05: k0=seg offset (mask 0x3)
+       andi    k0, NBPG-(1<<PTR_SCALESHIFT)    #05: k0=seg offset (mask 0x3)
        PTR_ADDU k1, k0, k1                     #06: k1=seg entry address
        PTR_L   k1, 0(k1)                       #07: k1=seg entry
        _MFC0   k0, MIPS_COP_0_BAD_VADDR        #08: k0=bad address (again)
        beq     k1, zero, 5f                    #09: ==0 -- no page table
+       PTR_SRL k0, (PGSHIFT-2)                 #0a: k0=VPN (aka va>>10)
+       andi    k0, k0, (NBPG-8)                #0b: k0=page tab offset
+       PTR_ADDU k1, k1, k0                     #0c: k1=pte address
+       INT_L   k0, 0(k1)                       #0d: k0=lo0 pte
+       INT_L   k1, 4(k1)                       #0e: k1=lo1 pte
+       _SLL    k0, WIRED_SHIFT                 #0f: chop top 2 bits (part 1a)
+       _SRL    k0, WIRED_SHIFT                 #10: chop top 2 bits (part 1b)
 #ifdef MIPS3_5900
        _MTC0   k0, MIPS_COP_0_TLB_LO0          #11: lo0 is loaded
        sync.p                                  #12: R5900 cop0 hazard