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[src/trunk]: src/sys/arch/arm Preliminary ARM11 MPCore support.
details: https://anonhg.NetBSD.org/src/rev/a8f0c245cf83
branches: trunk
changeset: 763091:a8f0c245cf83
user: bsh <bsh%NetBSD.org@localhost>
date: Thu Mar 10 07:47:14 2011 +0000
description:
Preliminary ARM11 MPCore support.
I have confirmed this commit doesn't affect existing evbarm kernels by
comparing binaries.
diffstat:
sys/arch/arm/arm/cpufunc.c | 139 ++++++++++++++++-
sys/arch/arm/arm32/pmap.c | 88 ++++++++++-
sys/arch/arm/conf/files.arm | 8 +-
sys/arch/arm/include/arm32/pmap.h | 94 +++++++++++-
sys/arch/arm/include/arm32/pte.h | 53 +++++-
sys/arch/arm/include/armreg.h | 17 +-
sys/arch/arm/include/cpuconf.h | 41 ++++-
sys/arch/arm/include/cpufunc.h | 6 +-
sys/arch/arm/mpcore/files.mpcore | 38 ++++
sys/arch/arm/mpcore/mpcore_a2x_io.S | 99 ++++++++++++
sys/arch/arm/mpcore/mpcore_a2x_space.c | 129 +++++++++++++++
sys/arch/arm/mpcore/mpcore_a4x_io.S | 99 ++++++++++++
sys/arch/arm/mpcore/mpcore_a4x_space.c | 129 +++++++++++++++
sys/arch/arm/mpcore/mpcore_axi.c | 182 ++++++++++++++++++++++
sys/arch/arm/mpcore/mpcore_clock.c | 208 +++++++++++++++++++++++++
sys/arch/arm/mpcore/mpcore_pmr.c | 119 ++++++++++++++
sys/arch/arm/mpcore/mpcore_space.c | 271 +++++++++++++++++++++++++++++++++
sys/arch/arm/mpcore/mpcorereg.h | 78 +++++++++
sys/arch/arm/mpcore/mpcorevar.h | 60 +++++++
19 files changed, 1835 insertions(+), 23 deletions(-)
diffs (truncated from 2212 to 300 lines):
diff -r 2b340cd0ed5d -r a8f0c245cf83 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Thu Mar 10 03:35:37 2011 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Thu Mar 10 07:47:14 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.101 2010/10/02 05:37:58 kiyohara Exp $ */
+/* $NetBSD: cpufunc.c,v 1.102 2011/03/10 07:47:14 bsh Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.101 2010/10/02 05:37:58 kiyohara Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.102 2011/03/10 07:47:14 bsh Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -794,6 +794,64 @@
};
#endif /* CPU_ARM1136 */
+#ifdef CPU_ARM11MPCORE
+struct cpu_functions arm11mpcore_cpufuncs = {
+ /* CPU functions */
+
+ .cf_id = cpufunc_id,
+ .cf_cpwait = cpufunc_nullop,
+
+ /* MMU functions */
+
+ .cf_control = cpufunc_control,
+ .cf_domains = cpufunc_domains,
+ .cf_setttb = arm11_setttb,
+ .cf_faultstatus = cpufunc_faultstatus,
+ .cf_faultaddress = cpufunc_faultaddress,
+
+ /* TLB functions */
+
+ .cf_tlb_flushID = arm11_tlb_flushID,
+ .cf_tlb_flushID_SE = arm11_tlb_flushID_SE,
+ .cf_tlb_flushI = arm11_tlb_flushI,
+ .cf_tlb_flushI_SE = arm11_tlb_flushI_SE,
+ .cf_tlb_flushD = arm11_tlb_flushD,
+ .cf_tlb_flushD_SE = arm11_tlb_flushD_SE,
+
+ /* Cache operations */
+
+ .cf_icache_sync_all = armv6_icache_sync_all,
+ .cf_icache_sync_range = armv5_icache_sync_range,
+
+ .cf_dcache_wbinv_all = armv6_dcache_wbinv_all,
+ .cf_dcache_wbinv_range = armv5_dcache_wbinv_range,
+ .cf_dcache_inv_range = armv5_dcache_inv_range,
+ .cf_dcache_wb_range = armv5_dcache_wb_range,
+
+ .cf_idcache_wbinv_all = armv6_idcache_wbinv_all,
+ .cf_idcache_wbinv_range = armv5_idcache_wbinv_range,
+
+ /* Other functions */
+
+ .cf_flush_prefetchbuf = cpufunc_nullop,
+ .cf_drain_writebuf = arm11_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
+
+ .cf_sleep = arm11_sleep,
+
+ /* Soft functions */
+
+ .cf_dataabt_fixup = cpufunc_null_fixup,
+ .cf_prefetchabt_fixup = cpufunc_null_fixup,
+
+ .cf_context_switch = arm11_context_switch,
+
+ .cf_setup = arm11mpcore_setup
+
+};
+#endif /* CPU_ARM11MPCORE */
+
#ifdef CPU_SA110
struct cpu_functions sa110_cpufuncs = {
/* CPU functions */
@@ -1563,6 +1621,28 @@
return 0;
}
#endif /* CPU_ARM10 */
+
+
+#if defined(CPU_ARM11MPCORE)
+ if (cputype == CPU_ID_ARM11MPCORE) {
+ cpufuncs = arm11mpcore_cpufuncs;
+ get_cachetype_cp15();
+ armv5_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
+ armv5_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
+ arm_dcache_l2_nsets)) - armv5_dcache_sets_inc;
+ armv5_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
+ armv5_dcache_index_max = 0U - armv5_dcache_index_inc;
+ cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
+ cpu_do_powersave = 1; /* Enable powersave */
+ pmap_pte_init_arm11mpcore();
+ if (arm_cache_prefer_mask)
+ uvmexp.ncolors = (arm_cache_prefer_mask >> PGSHIFT) + 1;
+
+ return 0;
+
+ }
+#endif /* CPU_ARM11MPCORE */
+
#if defined(CPU_ARM11)
if (cputype == CPU_ID_ARM1136JS ||
cputype == CPU_ID_ARM1136JSR1 ||
@@ -2624,6 +2704,61 @@
}
#endif /* CPU_ARM11 */
+#if defined(CPU_ARM11MPCORE)
+
+void
+arm11mpcore_setup(char *args)
+{
+ int cpuctrl, cpuctrlmask;
+
+#if defined(PROCESS_ID_IS_CURCPU)
+ /* set curcpu() */
+ __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
+#elif defined(PROCESS_ID_IS_CURLWP)
+ /* set curlwp() */
+ __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
+#endif
+
+ cpuctrl = CPU_CONTROL_IC_ENABLE
+ | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_BPRD_ENABLE ;
+ cpuctrlmask = CPU_CONTROL_IC_ENABLE
+ | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_BPRD_ENABLE
+ | CPU_CONTROL_AFLT_ENABLE
+ | CPU_CONTROL_VECRELOC;
+
+#ifdef ARM11MPCORE_MMU_COMPAT
+ /* XXX: S and R? */
+#endif
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+ cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+ cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl);
+
+ if (vector_page == ARM_VECTORS_HIGH)
+ cpuctrl |= CPU_CONTROL_VECRELOC;
+
+ /* Clear out the cache */
+ cpu_idcache_wbinv_all();
+
+ /* Now really make sure they are clean. */
+ __asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
+
+ /* Allow detection code to find the VFP if it's fitted. */
+ __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
+
+ /* Set the control register */
+ curcpu()->ci_ctrl = cpu_control(cpuctrlmask, cpuctrl);
+
+ /* And again. */
+ cpu_idcache_wbinv_all();
+}
+#endif /* CPU_ARM11MPCORE */
+
+
#if defined(CPU_CORTEX)
struct cpu_option armv7_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
diff -r 2b340cd0ed5d -r a8f0c245cf83 sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Thu Mar 10 03:35:37 2011 +0000
+++ b/sys/arch/arm/arm32/pmap.c Thu Mar 10 07:47:14 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.220 2011/02/28 10:03:49 macallan Exp $ */
+/* $NetBSD: pmap.c,v 1.221 2011/03/10 07:47:14 bsh Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -211,7 +211,7 @@
#include <machine/param.h>
#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.220 2011/02/28 10:03:49 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.221 2011/03/10 07:47:14 bsh Exp $");
#ifdef PMAP_DEBUG
@@ -6364,6 +6364,90 @@
}
#endif /* ARM_MMU_XSCALE == 1 */
+
+#if defined(CPU_ARM11MPCORE)
+
+void
+pmap_pte_init_arm11mpcore(void)
+{
+
+ /* cache mode is controlled by 5 bits (B, C, TEX) */
+ pte_l1_s_cache_mask = L1_S_CACHE_MASK_armv6;
+ pte_l2_l_cache_mask = L2_L_CACHE_MASK_armv6;
+#if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE)
+ /* use extended small page (without APn, with TEX) */
+ pte_l2_s_cache_mask = L2_XS_CACHE_MASK_armv6;
+#else
+ pte_l2_s_cache_mask = L2_S_CACHE_MASK_armv6c;
+#endif
+
+ /* write-back, write-allocate */
+ pte_l1_s_cache_mode = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01);
+ pte_l2_l_cache_mode = L2_C | L2_B | L2_V6_L_TEX(0x01);
+#if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE)
+ pte_l2_s_cache_mode = L2_C | L2_B | L2_V6_XS_TEX(0x01);
+#else
+ /* no TEX. read-allocate */
+ pte_l2_s_cache_mode = L2_C | L2_B;
+#endif
+ /*
+ * write-back, write-allocate for page tables.
+ */
+ pte_l1_s_cache_mode_pt = L1_S_C | L1_S_B | L1_S_V6_TEX(0x01);
+ pte_l2_l_cache_mode_pt = L2_C | L2_B | L2_V6_L_TEX(0x01);
+#if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE)
+ pte_l2_s_cache_mode_pt = L2_C | L2_B | L2_V6_XS_TEX(0x01);
+#else
+ pte_l2_s_cache_mode_pt = L2_C | L2_B;
+#endif
+
+ pte_l1_s_prot_u = L1_S_PROT_U_armv6;
+ pte_l1_s_prot_w = L1_S_PROT_W_armv6;
+ pte_l1_s_prot_ro = L1_S_PROT_RO_armv6;
+ pte_l1_s_prot_mask = L1_S_PROT_MASK_armv6;
+
+#if defined(ARM11MPCORE_COMPAT_MMU) || defined(ARMV6_EXTENDED_SMALL_PAGE)
+ pte_l2_s_prot_u = L2_S_PROT_U_armv6n;
+ pte_l2_s_prot_w = L2_S_PROT_W_armv6n;
+ pte_l2_s_prot_ro = L2_S_PROT_RO_armv6n;
+ pte_l2_s_prot_mask = L2_S_PROT_MASK_armv6n;
+
+#else
+ /* with AP[0..3] */
+ pte_l2_s_prot_u = L2_S_PROT_U_generic;
+ pte_l2_s_prot_w = L2_S_PROT_W_generic;
+ pte_l2_s_prot_ro = L2_S_PROT_RO_generic;
+ pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
+#endif
+
+#ifdef ARM11MPCORE_COMPAT_MMU
+ /* with AP[0..3] */
+ pte_l2_l_prot_u = L2_L_PROT_U_generic;
+ pte_l2_l_prot_w = L2_L_PROT_W_generic;
+ pte_l2_l_prot_ro = L2_L_PROT_RO_generic;
+ pte_l2_l_prot_mask = L2_L_PROT_MASK_generic;
+
+ pte_l1_s_proto = L1_S_PROTO_armv6;
+ pte_l1_c_proto = L1_C_PROTO_armv6;
+ pte_l2_s_proto = L2_S_PROTO_armv6c;
+#else
+ pte_l2_l_prot_u = L2_L_PROT_U_armv6n;
+ pte_l2_l_prot_w = L2_L_PROT_W_armv6n;
+ pte_l2_l_prot_ro = L2_L_PROT_RO_armv6n;
+ pte_l2_l_prot_mask = L2_L_PROT_MASK_armv6n;
+
+ pte_l1_s_proto = L1_S_PROTO_armv6;
+ pte_l1_c_proto = L1_C_PROTO_armv6;
+ pte_l2_s_proto = L2_S_PROTO_armv6n;
+#endif
+
+ pmap_copy_page_func = pmap_copy_page_generic;
+ pmap_zero_page_func = pmap_zero_page_generic;
+ pmap_needs_pte_sync = 1;
+}
+#endif /* CPU_ARM11MPCORE */
+
+
#if ARM_MMU_V7 == 1
void
pmap_pte_init_armv7(void)
diff -r 2b340cd0ed5d -r a8f0c245cf83 sys/arch/arm/conf/files.arm
--- a/sys/arch/arm/conf/files.arm Thu Mar 10 03:35:37 2011 +0000
+++ b/sys/arch/arm/conf/files.arm Thu Mar 10 07:47:14 2011 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.100 2010/10/02 05:37:58 kiyohara Exp $
+# $NetBSD: files.arm,v 1.101 2011/03/10 07:47:14 bsh Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -15,6 +15,7 @@
CPU_SHEEVA
defflag opt_cputypes.h CPU_ARM1136: CPU_ARM11
defflag opt_cputypes.h CPU_ARM1176: CPU_ARM11
+defflag opt_cputypes.h CPU_ARM11MPCORE: CPU_ARM11
defflag opt_cputypes.h CPU_CORTEXA8: CPU_CORTEX
defflag opt_cputypes.h CPU_CORTEXA9: CPU_CORTEX
defflag opt_cputypes.h FPU_VFP
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