Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src Turn PMAP_NOCACHE into MI flag.
details: https://anonhg.NetBSD.org/src/rev/74e86e644e02
branches: trunk
changeset: 756107:74e86e644e02
user: cegger <cegger%NetBSD.org@localhost>
date: Tue Jul 06 20:50:33 2010 +0000
description:
Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.
hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.
x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.
Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html
No comments on this last version.
diffstat:
share/man/man9/pmap.9 | 32 +++++++++++++++-
sys/arch/amd64/include/pte.h | 22 +++++------
sys/arch/hppa/include/pmap.h | 7 +---
sys/arch/i386/include/pte.h | 18 ++++-----
sys/arch/mips/include/pmap.h | 4 +-
sys/arch/mips/mips/pmap.c | 11 +++--
sys/arch/sgimips/sgimips/bus.c | 19 ++++-----
sys/arch/x86/include/cpuvar.h | 5 +-
sys/arch/x86/include/pmap.h | 3 +-
sys/arch/x86/include/pte.h | 50 ++++++++++++++++++++++++++
sys/arch/x86/include/specialreg.h | 3 +-
sys/arch/x86/x86/bus_space.c | 24 ++++++------
sys/arch/x86/x86/cpu.c | 5 +-
sys/arch/x86/x86/pmap.c | 75 +++++++++++++++++++++++++++++++++++---
sys/arch/xen/x86/cpu.c | 5 +-
15 files changed, 210 insertions(+), 73 deletions(-)
diffs (truncated from 640 to 300 lines):
diff -r 2ac4fff19dcb -r 74e86e644e02 share/man/man9/pmap.9
--- a/share/man/man9/pmap.9 Tue Jul 06 18:22:20 2010 +0000
+++ b/share/man/man9/pmap.9 Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-.\" $NetBSD: pmap.9,v 1.42 2010/03/22 18:58:33 joerg Exp $
+.\" $NetBSD: pmap.9,v 1.43 2010/07/06 20:50:33 cegger Exp $
.\"
.\" Copyright (c) 2000, 2001, 2002 The NetBSD Foundation, Inc.
.\" All rights reserved.
@@ -486,8 +486,23 @@
.Nm
module must panic.
.It PMAP_NOCACHE
-The mapping being created is not cached.
+The mapping being created is
+.Em not
+cached.
Write accesses have a write-through policy.
+No speculative memory accesses.
+.It PMAP_WRITE_COMBINE
+The mapping being created is
+.Em not
+cached.
+Writes are combined and done in one burst.
+Speculative read accesses may be allowed.
+.It PMAP_WRITE_BACK
+All accesses to the created mapping are cached.
+On reads, cachelines become shared or exclusive if allocated on cache miss.
+On writes, cachelines become modified on a cache miss.
+.It PMAP_NOCACHE_OVR
+Same as PMAP_NOCACHE but mapping is overrideable (e.g. on x86 by MTRRs).
.El
.Pp
The access type provided in the
@@ -633,6 +648,19 @@
.Em not
cached.
Write accesses have a write-through policy.
+No speculative memory accesses.
+.It PMAP_WRITE_COMBINE
+The mapping being created is
+.Em not
+cached.
+Writes are combined and done in one burst.
+Speculative read accesses may be allowed.
+.It PMAP_WRITE_BACK
+All accesses to the created mapping are cached.
+On reads, cachelines become shared or exclusive if allocated on cache miss.
+On writes, cachelines become modified on a cache miss.
+.It PMAP_NOCACHE_OVR
+Same as PMAP_NOCACHE but mapping is overrideable (e.g. on x86 by MTRRs).
.El
.Pp
Mappings of this type are always
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/amd64/include/pte.h
--- a/sys/arch/amd64/include/pte.h Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/amd64/include/pte.h Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.6 2010/02/26 19:25:07 jym Exp $ */
+/* $NetBSD: pte.h,v 1.7 2010/07/06 20:50:34 cegger Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -105,18 +105,23 @@
#define PG_RW 0x0000000000000002 /* read-write */
#define PG_u 0x0000000000000004 /* user accessible */
#define PG_PROT 0x0000000000000006
-#define PG_N 0x0000000000000018 /* non-cacheable */
+#define PG_WT 0x0000000000000008 /* write-through */
+#define PG_N 0x0000000000000010 /* non-cacheable */
#define PG_U 0x0000000000000020 /* used */
#define PG_M 0x0000000000000040 /* modified */
-#define PG_PS 0x0000000000000080 /* 2MB page size */
+#define PG_PAT 0x0000000000000080 /* PAT (on pte) */
+#define PG_PS 0x0000000000000080 /* 2MB page size (on pde) */
#define PG_G 0x0000000000000100 /* not flushed */
#define PG_AVAIL1 0x0000000000000200
#define PG_AVAIL2 0x0000000000000400
#define PG_AVAIL3 0x0000000000000800
+#define PG_LGPAT 0x0000000000001000 /* PAT on large pages */
#define PG_FRAME 0x000ffffffffff000
#define PG_NX 0x8000000000000000
-#define PG_LGFRAME 0x000fffffffe00000 /* large (2M) page frame mask */
+#define PG_2MFRAME 0x000fffffffe00000 /* large (2M) page frame mask */
+#define PG_1GFRAME 0x000fffffc0000000 /* large (1G) page frame mask */
+#define PG_LGFRAME PG_2MFRAME
/*
* short forms of protection codes
@@ -125,13 +130,6 @@
#define PG_KR 0x0000000000000000 /* kernel read-only */
#define PG_KW 0x0000000000000002 /* kernel read-write */
-/*
- * page protection exception bits
- */
-
-#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
-#define PGEX_W 0x02 /* exception during a write cycle */
-#define PGEX_U 0x04 /* exception while in user mode (upl) */
-#define PGEX_X 0x10 /* exception during instruction fetch */
+#include <x86/pte.h>
#endif /* _AMD64_PTE_H_ */
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/hppa/include/pmap.h
--- a/sys/arch/hppa/include/pmap.h Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/hppa/include/pmap.h Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.27 2010/06/21 14:43:34 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.28 2010/07/06 20:50:34 cegger Exp $ */
/* $OpenBSD: pmap.h,v 1.35 2007/12/14 18:32:23 deraadt Exp $ */
@@ -192,11 +192,6 @@
((((va) & 0xc0000000) != 0xc0000000) ? \
(pmap)->pm_space : HPPA_SID_KERNEL)
-/*
- * MD flags that we use for pmap_kenter_pa:
- */
-#define PMAP_NOCACHE 0x01000000 /* set the non-cacheable bit */
-
#endif /* _KERNEL */
#endif /* _HPPA_PMAP_H_ */
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/i386/include/pte.h
--- a/sys/arch/i386/include/pte.h Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/i386/include/pte.h Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.23 2010/05/04 23:27:14 jym Exp $ */
+/* $NetBSD: pte.h,v 1.24 2010/07/06 20:50:34 cegger Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -218,7 +218,9 @@
/* macros to get real L2 and L3 index, from our "extended" L2 index */
#define l2tol3(idx) ((idx) >> (L3_SHIFT - L2_SHIFT))
#define l2tol2(idx) ((idx) & (L2_REALMASK >> L2_SHIFT))
+
#else /* PAE */
+
#define L1_SHIFT 12
#define L2_SHIFT 22
#define NBPD_L1 (1UL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
@@ -245,14 +247,17 @@
#define PG_RW 0x00000002 /* read-write page */
#define PG_u 0x00000004 /* user accessible page */
#define PG_PROT 0x00000806 /* all protection bits */
-#define PG_N 0x00000018 /* non-cacheable */
+#define PG_WT 0x00000008 /* write through */
+#define PG_N 0x00000010 /* non-cacheable */
#define PG_U 0x00000020 /* has been used */
#define PG_M 0x00000040 /* has been modified */
+#define PG_PAT 0x00000080 /* PAT (on pte) */
#define PG_PS 0x00000080 /* 4MB page size */
#define PG_G 0x00000100 /* global, don't TLB flush */
#define PG_AVAIL1 0x00000200 /* ignored by hardware */
#define PG_AVAIL2 0x00000400 /* ignored by hardware */
#define PG_AVAIL3 0x00000800 /* ignored by hardware */
+#define PG_LGPAT 0x00001000 /* PAT on large pages */
/*
* various short-hand protection codes
@@ -267,13 +272,6 @@
#define PG_NX 0 /* dummy */
#endif
-/*
- * page protection exception bits
- */
-
-#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
-#define PGEX_W 0x02 /* exception during a write cycle */
-#define PGEX_U 0x04 /* exception while in user mode (upl) */
-#define PGEX_X 0x10 /* exception during instruction fetch */
+#include <x86/pte.h>
#endif /* _I386_PTE_H_ */
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/mips/include/pmap.h
--- a/sys/arch/mips/include/pmap.h Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/mips/include/pmap.h Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.57 2009/12/14 00:46:05 matt Exp $ */
+/* $NetBSD: pmap.h,v 1.58 2010/07/06 20:50:34 cegger Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -202,7 +202,7 @@
#define PMAP_CCA_FOR_PA(pa) CCA_UNCACHED /* uncached */
#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
-#define PMAP_NOCACHE 0x4000000000000000ULL
+#define PGC_NOCACHE 0x4000000000000000ULL
#endif
#endif /* _KERNEL */
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/mips/mips/pmap.c
--- a/sys/arch/mips/mips/pmap.c Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/mips/mips/pmap.c Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.188 2009/12/14 00:46:07 matt Exp $ */
+/* $NetBSD: pmap.c,v 1.189 2010/07/06 20:50:34 cegger Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@@ -67,7 +67,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.188 2009/12/14 00:46:07 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.189 2010/07/06 20:50:34 cegger Exp $");
/*
* Manages physical address maps.
@@ -1177,9 +1177,12 @@
#endif
#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
- if (pa & PMAP_NOCACHE) {
+ if (flags & PMAP_NOCACHE) {
cached = 0;
- pa &= ~PMAP_NOCACHE;
+ pa &= ~PGC_NOCACHE;
+ } else {
+ cached = 1;
+ pa |= PGC_NOCACHE;
}
#endif
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/sgimips/sgimips/bus.c
--- a/sys/arch/sgimips/sgimips/bus.c Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/sgimips/sgimips/bus.c Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus.c,v 1.59 2009/12/17 03:59:31 macallan Exp $ */
+/* $NetBSD: bus.c,v 1.60 2010/07/06 20:50:35 cegger Exp $ */
/*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.59 2009/12/17 03:59:31 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus.c,v 1.60 2010/07/06 20:50:35 cegger Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1116,6 +1116,7 @@
int curseg;
const uvm_flag_t kmflags =
(flags & BUS_DMA_NOWAIT) != 0 ? UVM_KMF_NOWAIT : 0;
+ u_int pmapflags;
/*
* If we're only mapping 1 segment, use KSEG0 or KSEG1, to avoid
@@ -1139,21 +1140,19 @@
*kvap = (void *)va;
+ pmapflags = VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED;
+ if (flags & BUS_DMA_COHERENT)
+ pmapflags |= PMAP_NOCACHE;
+
for (curseg = 0; curseg < nsegs; curseg++) {
for (addr = segs[curseg].ds_addr;
addr < (segs[curseg].ds_addr + segs[curseg].ds_len);
addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) {
if (size == 0)
panic("_bus_dmamem_map: size botch");
- pmap_enter(pmap_kernel(), va,
-#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
- (flags & BUS_DMA_COHERENT) ?
- addr | PMAP_NOCACHE : addr,
-#else
- addr,
-#endif
+ pmap_enter(pmap_kernel(), va, addr,
VM_PROT_READ | VM_PROT_WRITE,
- VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED);
+ pmapflags);
}
}
pmap_update(pmap_kernel());
diff -r 2ac4fff19dcb -r 74e86e644e02 sys/arch/x86/include/cpuvar.h
--- a/sys/arch/x86/include/cpuvar.h Tue Jul 06 18:22:20 2010 +0000
+++ b/sys/arch/x86/include/cpuvar.h Tue Jul 06 20:50:33 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuvar.h,v 1.32 2010/04/18 23:47:51 jym Exp $ */
+/* $NetBSD: cpuvar.h,v 1.33 2010/07/06 20:50:35 cegger Exp $ */
/*-
* Copyright (c) 2000, 2007 The NetBSD Foundation, Inc.
@@ -140,12 +140,13 @@
#endif
void cpu_get_tsc_freq(struct cpu_info *);
+void pat_init(struct cpu_info *);
extern int cpu_vendor;
Home |
Main Index |
Thread Index |
Old Index