[src/trunk]: src/sys/arch/mips/mips - clear MIPS_FPU_EXCEPTION_BITS in MIPS_F...

[tsutsui <tsutsui%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/db6949df7e36
branches:  trunk
changeset: 762727:db6949df7e36
user:      tsutsui <tsutsui%NetBSD.org@localhost>
date:      Sat Feb 26 13:58:34 2011 +0000

description:
- clear MIPS_FPU_EXCEPTION_BITS in MIPS_FPU_CSR in SIGILL case
  as noted in commit log of rev 1.158
- update comment to reflect changes in rev 1.109

diffstat:

 sys/arch/mips/mips/locore.S |  11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diffs (35 lines):

diff -r d96c5d1cdbb0 -r db6949df7e36 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S       Sat Feb 26 12:56:35 2011 +0000
+++ b/sys/arch/mips/mips/locore.S       Sat Feb 26 13:58:34 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.182 2011/02/26 09:47:24 tsutsui Exp $     */
+/*     $NetBSD: locore.S,v 1.183 2011/02/26 13:58:34 tsutsui Exp $     */
 
 /*
  * Copyright (c) 1992, 1993
@@ -645,12 +645,12 @@
  * Check to see if the instruction to be emulated is a floating-point
  * instruction.
  */
-       srl             t0, a0, MIPS_OPCODE_SHIFT
-       beq             t0, MIPS_OPCODE_C1, 4f
+       srl             t2, a0, MIPS_OPCODE_SHIFT
+       beq             t2, MIPS_OPCODE_C1, 4f
         nop
 
 /*
- * Send a floating point exception signal to the current LWP.
+ * Send an ILL signal to the current LWP if the instruction can't be emulated.
  */
        srl             a2, 8
        sll             a2, 8
@@ -659,6 +659,9 @@
        REG_S           a2, TF_REG_CAUSE(a1)
        REG_EPILOGUE
 
+       and             t2, t0, ~MIPS_FPU_EXCEPTION_BITS
+       ctc1            t2, MIPS_FPU_CSR
+
        move            a1, a0                          # code = instruction
        jal             _C_LABEL(mips_fpuillinst)
         move           a0, MIPS_CURLWP                 # get current LWP