[src/trunk]: src/sys/arch/powerpc/include add access functions for the Instru...

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0f5d66cf1984
branches:  trunk
changeset: 764787:0f5d66cf1984
user:      macallan <macallan%NetBSD.org@localhost>
date:      Wed May 04 04:33:37 2011 +0000

description:
add access functions for the Instruction Cache Throttling Control register
found in 750 and newer CPUs

diffstat:

 sys/arch/powerpc/include/cpu.h |  24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

diffs (38 lines):

diff -r 0646e196d934 -r 0f5d66cf1984 sys/arch/powerpc/include/cpu.h
--- a/sys/arch/powerpc/include/cpu.h    Wed May 04 03:43:30 2011 +0000
+++ b/sys/arch/powerpc/include/cpu.h    Wed May 04 04:33:37 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.h,v 1.75 2011/02/16 18:42:33 matt Exp $    */
+/*     $NetBSD: cpu.h,v 1.76 2011/05/04 04:33:37 macallan Exp $        */
 
 /*
  * Copyright (C) 1999 Wolfgang Solfrank.
@@ -322,6 +322,28 @@
        return (cnt);
 }
 
+/*
+ * functions to access the G3's cache throttling register
+ * bits 1 - 9 specify additional waits on cache acess
+ * bit 0 enables cache throttling
+ */
+
+static __inline int
+mfictc(void)
+{
+       int reg;
+
+       __asm ("mfspr %0,1019" : "=r"(reg));
+       return reg;
+}
+
+static __inline void
+mtictc(uint32_t reg)
+{
+
+       __asm ("mtspr 1019,%0" :: "r"(reg));
+}
+
 #define        CLKF_USERMODE(frame)    (((frame)->cf_srr1 & PSL_PR) != 0)
 #define        CLKF_PC(frame)          ((frame)->cf_srr0)
 #define        CLKF_INTR(frame)        ((frame)->cf_idepth > 0)