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[src/trunk]: src/external/gpl3/binutils/dist Pull in MIPS XLR (XLS) support f...
details: https://anonhg.NetBSD.org/src/rev/0f7b59022046
branches: trunk
changeset: 764235:0f7b59022046
user: matt <matt%NetBSD.org@localhost>
date: Thu Apr 14 07:49:48 2011 +0000
description:
Pull in MIPS XLR (XLS) support from patch in
http://sourceware.org/ml/binutils/2009-01/msg00383.html
This replaces local changes to support some xlr instructions.
diffstat:
external/gpl3/binutils/dist/bfd/aoutx.h | 1 +
external/gpl3/binutils/dist/bfd/archures.c | 1 +
external/gpl3/binutils/dist/bfd/bfd-in2.h | 1 +
external/gpl3/binutils/dist/bfd/cpu-mips.c | 6 +-
external/gpl3/binutils/dist/bfd/elfxx-mips.c | 8 +
external/gpl3/binutils/dist/binutils/readelf.c | 1 +
external/gpl3/binutils/dist/gas/config/tc-mips.c | 40 ++++++++
external/gpl3/binutils/dist/gas/config/tc-vax.h | 8 -
external/gpl3/binutils/dist/gas/doc/c-mips.texi | 3 +-
external/gpl3/binutils/dist/gas/testsuite/gas/mips/mips.exp | 3 +
external/gpl3/binutils/dist/gas/testsuite/gas/mips/xlr-ext.d | 20 ++++
external/gpl3/binutils/dist/gas/testsuite/gas/mips/xlr-ext.s | 27 +++++
external/gpl3/binutils/dist/include/elf/mips.h | 1 +
external/gpl3/binutils/dist/include/opcode/mips.h | 11 ++-
external/gpl3/binutils/dist/opcodes/mips-dis.c | 56 ++++++++++++
external/gpl3/binutils/dist/opcodes/mips-opc.c | 20 +++-
16 files changed, 190 insertions(+), 17 deletions(-)
diffs (truncated from 474 to 300 lines):
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/bfd/aoutx.h
--- a/external/gpl3/binutils/dist/bfd/aoutx.h Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/bfd/aoutx.h Thu Apr 14 07:49:48 2011 +0000
@@ -793,6 +793,7 @@
case bfd_mach_mipsisa64:
case bfd_mach_mipsisa64r2:
case bfd_mach_mips_sb1:
+ case bfd_mach_mips_xlr:
/* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
arch_flags = M_MIPS2;
break;
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/bfd/archures.c
--- a/external/gpl3/binutils/dist/bfd/archures.c Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/bfd/archures.c Thu Apr 14 07:49:48 2011 +0000
@@ -173,6 +173,7 @@
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mips_octeon 6501
+.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/bfd/bfd-in2.h
--- a/external/gpl3/binutils/dist/bfd/bfd-in2.h Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/bfd/bfd-in2.h Thu Apr 14 07:49:48 2011 +0000
@@ -1795,6 +1795,7 @@
#define bfd_mach_mips_loongson_2f 3002
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
+#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/bfd/cpu-mips.c
--- a/external/gpl3/binutils/dist/bfd/cpu-mips.c Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/bfd/cpu-mips.c Thu Apr 14 07:49:48 2011 +0000
@@ -89,7 +89,8 @@
I_sb1,
I_loongson_2e,
I_loongson_2f,
- I_mipsocteon
+ I_mipsocteon,
+ I_xlr
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -125,7 +126,8 @@
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
- N (64, 64, bfd_mach_mips_octeon, "mips:octeon", FALSE, 0)
+ N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
+ N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0)
};
/* The default architecture is mips:3000, but with a machine number of
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/bfd/elfxx-mips.c
--- a/external/gpl3/binutils/dist/bfd/elfxx-mips.c Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/bfd/elfxx-mips.c Thu Apr 14 07:49:48 2011 +0000
@@ -5878,6 +5878,9 @@
case E_MIPS_MACH_OCTEON:
return bfd_mach_mips_octeon;
+ case E_MIPS_MACH_XLR:
+ return bfd_mach_mips_xlr;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -10436,6 +10439,10 @@
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
break;
+ case bfd_mach_mips_xlr:
+ val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
@@ -12131,6 +12138,7 @@
/* MIPS64 extensions. */
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
+ { bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
/* MIPS V extensions. */
{ bfd_mach_mipsisa64, bfd_mach_mips5 },
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/binutils/readelf.c
--- a/external/gpl3/binutils/dist/binutils/readelf.c Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/binutils/readelf.c Thu Apr 14 07:49:48 2011 +0000
@@ -2207,6 +2207,7 @@
case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
+ case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
case 0:
/* We simply ignore the field in this case to avoid confusion:
MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/gas/config/tc-mips.c
--- a/external/gpl3/binutils/dist/gas/config/tc-mips.c Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/gas/config/tc-mips.c Thu Apr 14 07:49:48 2011 +0000
@@ -6031,6 +6031,43 @@
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
break;
+ case M_MSGSND:
+ {
+ unsigned long temp = (treg << 16) | (0x01);
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGLD:
+ {
+ unsigned long temp = (0x02);
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGLD_T:
+ {
+ unsigned long temp = (treg << 16) | (0x02);
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGWAIT:
+ macro_build (NULL, "c2", "C", 3);
+ /* AT is not used, just return */
+ return;
+
+ case M_MSGWAIT_T:
+ {
+ unsigned long temp = (treg << 16) | 0x03;
+ macro_build (NULL, "c2", "C", temp);
+ }
+ /* AT is not used, just return */
+ return;
+
case M_J_A:
/* The j instruction may not be used in PIC code, since it
requires an absolute address. We convert it to a b
@@ -15174,6 +15211,9 @@
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
+ /* RMI Xlr */
+ { "xlr", 0, ISA_MIPS64, CPU_XLR },
+
/* End marker */
{ NULL, 0, 0, 0 }
};
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/gas/config/tc-vax.h
--- a/external/gpl3/binutils/dist/gas/config/tc-vax.h Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/gas/config/tc-vax.h Thu Apr 14 07:49:48 2011 +0000
@@ -54,14 +54,6 @@
void vax_cons_fix_new (struct frag *, int, unsigned int, struct expressionS *);
#endif
-#ifdef OBJ_ELF
-#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) vax_cons (EXP, NBYTES)
-#define TC_CONS_FIX_NEW vax_cons_fix_new
-void vax_cons PARAMS ((expressionS *, int));
-void vax_cons_fix_new
- PARAMS ((struct frag *, int, unsigned int, struct expressionS *));
-#endif
-
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/gas/doc/c-mips.texi
--- a/external/gpl3/binutils/dist/gas/doc/c-mips.texi Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/gas/doc/c-mips.texi Thu Apr 14 07:49:48 2011 +0000
@@ -274,7 +274,8 @@
sb1a,
loongson2e,
loongson2f,
-octeon
+octeon,
+xlr
@end quotation
For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/gas/testsuite/gas/mips/mips.exp
--- a/external/gpl3/binutils/dist/gas/testsuite/gas/mips/mips.exp Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/gas/testsuite/gas/mips/mips.exp Thu Apr 14 07:49:48 2011 +0000
@@ -364,6 +364,8 @@
mips_arch_create octeon 64 mips64r2 {} \
{ -march=octeon -mtune=octeon } { -mmips:octeon } \
{ mips64octeon*-*-* }
+mips_arch_create xlr 64 mips64 {} \
+ { -march=xlr -mtune=xlr } { -mmips:xlr }
#
# And now begin the actual tests! VxWorks uses RELA rather than REL
@@ -588,6 +590,7 @@
run_dump_test "mips64-mdmx"
run_dump_test "sb1-ext-mdmx"
run_dump_test "sb1-ext-ps"
+ run_dump_test "xlr-ext"
}
run_dump_test "relax"
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/gas/testsuite/gas/mips/xlr-ext.d
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/gpl3/binutils/dist/gas/testsuite/gas/mips/xlr-ext.d Thu Apr 14 07:49:48 2011 +0000
@@ -0,0 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:xlr
+#name: XLRs native MIPS64 extensions
+#as: -march=xlr
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 3c000000 lui zero,0x0
+0+0004 <[^>]*> 8c010001 lw at,1\(zero\)
+0+0008 <[^>]*> 8c020002 lw v0,2\(zero\)
+0+000c <[^>]*> 70221838 daddwc v1,at,v0
+0+0010 <[^>]*> 70230010 ldaddw v1,at
+0+0014 <[^>]*> 70230011 ldaddwu v1,at
+0+0018 <[^>]*> 70230012 ldaddd v1,at
+0+001c <[^>]*> 70230014 swapw v1,at
+0+0020 <[^>]*> 70230015 swapwu v1,at
+0+0024 <[^>]*> 4a000003 c2 0x3
+0+0028 <[^>]*> 4a000002 c2 0x2
+0+002c <[^>]*> 4a000001 c2 0x1
+ \.\.\.
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/gas/testsuite/gas/mips/xlr-ext.s
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/gpl3/binutils/dist/gas/testsuite/gas/mips/xlr-ext.s Thu Apr 14 07:49:48 2011 +0000
@@ -0,0 +1,27 @@
+# Source file used to test XLR's assembler instructions
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+text_label:
+
+ lui $0, 0x00
+ lw $1, 0x01
+ lw $2, 0x02
+
+ daddwc $3, $1, $2
+
+ ldaddw $3, $1
+ ldaddwu $3, $1
+ ldaddd $3, $1
+
+ swapw $3, $1
+ swapwu $3, $1
+
+ msgwait
+ msgld $0
+ msgsnd $0
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/include/elf/mips.h
--- a/external/gpl3/binutils/dist/include/elf/mips.h Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/include/elf/mips.h Thu Apr 14 07:49:48 2011 +0000
@@ -214,6 +214,7 @@
#define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_SB1 0x008a0000
#define E_MIPS_MACH_OCTEON 0x008b0000
+#define E_MIPS_MACH_XLR 0x008c0000
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
diff -r 675e0eed399e -r 0f7b59022046 external/gpl3/binutils/dist/include/opcode/mips.h
--- a/external/gpl3/binutils/dist/include/opcode/mips.h Thu Apr 14 07:06:52 2011 +0000
+++ b/external/gpl3/binutils/dist/include/opcode/mips.h Thu Apr 14 07:49:48 2011 +0000
@@ -542,7 +542,7 @@
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0800
+#define INSN_CHIP_MASK 0xc3ff0820
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
@@ -591,6 +591,8 @@
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* RMI Xlr instruction */
+#define INSN_XLR 0x00000020
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -641,6 +643,7 @@
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON 6501
+#define CPU_XLR 887682 /* decimal 'XLR' */
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