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[src/trunk]: src/sys/arch/mips/mips - add mips_watchpoint_init() to discover ...
details: https://anonhg.NetBSD.org/src/rev/72e09faf432e
branches: trunk
changeset: 764209:72e09faf432e
user: cliff <cliff%NetBSD.org@localhost>
date: Thu Apr 14 05:10:04 2011 +0000
description:
- add mips_watchpoint_init() to discover number of CPU watchpoints,
and call that from {mips32,mips32r2,mips64,mips64r2}_vector_init()
diffstat:
sys/arch/mips/mips/mips_machdep.c | 27 +++++++++++++++++++++++++--
1 files changed, 25 insertions(+), 2 deletions(-)
diffs (80 lines):
diff -r cadbc567c2bc -r 72e09faf432e sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Thu Apr 14 05:09:34 2011 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Thu Apr 14 05:10:04 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.238 2011/04/06 05:50:39 matt Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.239 2011/04/14 05:10:04 cliff Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -112,7 +112,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.238 2011/04/06 05:50:39 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.239 2011/04/14 05:10:04 cliff Exp $");
#define __INTR_PRIVATE
#include "opt_cputype.h"
@@ -188,6 +188,10 @@
u_long cpu_dump_mempagecnt(void);
int cpu_dump(void);
+#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
+static void mips_watchpoint_init(void);
+#endif
+
#if defined(MIPS3_PLUS)
uint32_t mips3_cp0_tlb_page_mask_probe(void);
uint64_t mips3_cp0_tlb_entry_hi_probe(void);
@@ -784,6 +788,8 @@
/* Clear BEV in SR so we start handling our own exceptions */
mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
+
+ mips_watchpoint_init();
}
#endif /* MIPS32 */
@@ -849,6 +855,8 @@
/* Clear BEV in SR so we start handling our own exceptions */
mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
+
+ mips_watchpoint_init();
}
#endif /* MIPS32R2 */
@@ -902,6 +910,8 @@
/* Clear BEV in SR so we start handling our own exceptions */
mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
+
+ mips_watchpoint_init();
}
#endif /* MIPS64 */
@@ -972,6 +982,8 @@
/* Clear BEV in SR so we start handling our own exceptions */
mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
+
+ mips_watchpoint_init();
}
#endif /* MIPS64R2 */
@@ -2196,3 +2208,14 @@
KASSERT(ci->ci_cpl == IPL_NONE);
}
#endif /* PARANOIA */
+
+#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
+static void
+mips_watchpoint_init(void)
+{
+ /*
+ * determine number of CPU watchpoints
+ */
+ curcpu()->ci_cpuwatch_count = cpuwatch_discover();
+}
+#endif
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