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[src/trunk]: src/sys/arch Merge from matt-nb5-mips64.
details: https://anonhg.NetBSD.org/src/rev/17af4568f0a5
branches: trunk
changeset: 762363:17af4568f0a5
user: matt <matt%NetBSD.org@localhost>
date: Sun Feb 20 07:47:38 2011 +0000
description:
Merge from matt-nb5-mips64.
Add pci support.
new interrupt code.
Adapt to new world order for MIPS
diffstat:
sys/arch/mips/sibyte/dev/sbbuswatch.c | 112 ++++++++
sys/arch/mips/sibyte/dev/sbbuswatchvar.h | 36 ++
sys/arch/mips/sibyte/dev/sbmac.c | 6 +-
sys/arch/mips/sibyte/dev/sbobio.c | 8 +-
sys/arch/mips/sibyte/dev/sbobiovar.h | 8 +-
sys/arch/mips/sibyte/dev/sbscd.c | 8 +-
sys/arch/mips/sibyte/dev/sbscdvar.h | 9 +-
sys/arch/mips/sibyte/dev/sbscn.c | 6 +-
sys/arch/mips/sibyte/dev/sbtimer.c | 16 +-
sys/arch/mips/sibyte/dev/sbwdog.c | 24 +-
sys/arch/sbmips/conf/GENERIC | 46 ++-
sys/arch/sbmips/conf/GENERIC.MP | 11 +
sys/arch/sbmips/conf/GENERIC64.MP | 11 +
sys/arch/sbmips/conf/files.sbmips | 4 +-
sys/arch/sbmips/include/bus.h | 19 +-
sys/arch/sbmips/include/cpu.h | 2 +-
sys/arch/sbmips/include/cpuvar.h | 21 +
sys/arch/sbmips/include/intr.h | 97 ++-----
sys/arch/sbmips/include/pci_machdep.h | 3 +
sys/arch/sbmips/include/systemsw.h | 14 +-
sys/arch/sbmips/include/types.h | 4 +-
sys/arch/sbmips/include/vmparam.h | 15 +-
sys/arch/sbmips/sbmips/autoconf.c | 10 +-
sys/arch/sbmips/sbmips/cpu.c | 125 ++++++---
sys/arch/sbmips/sbmips/machdep.c | 79 +----
sys/arch/sbmips/sbmips/rtc.c | 42 +-
sys/arch/sbmips/sbmips/sb1250_icu.c | 396 +++++++++++++++++++++---------
sys/arch/sbmips/sbmips/systemsw.c | 20 +-
sys/arch/sbmips/sbmips/zbbus.c | 20 +-
sys/arch/sbmips/stand/Makefile | 6 +-
sys/arch/sbmips/stand/Makefile.bootprogs | 12 +-
sys/arch/sbmips/stand/Makefile.bootxx | 3 +-
sys/arch/sbmips/stand/boot/Makefile | 3 +-
sys/arch/sbmips/stand/netboot/Makefile | 3 +-
34 files changed, 775 insertions(+), 424 deletions(-)
diffs (truncated from 2130 to 300 lines):
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbbuswatch.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/sibyte/dev/sbbuswatch.c Sun Feb 20 07:47:38 2011 +0000
@@ -0,0 +1,112 @@
+/* $NetBSD: sbbuswatch.c,v 1.2 2011/02/20 07:47:39 matt Exp $ */
+/*
+ * Copyright (c) 2010, The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Cliff Neighbors.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/cpu.h>
+
+#include <mips/cpu.h>
+#include <mips/locore.h>
+
+#include <mips/sibyte/include/sb1250_int.h>
+#include <mips/sibyte/include/sb1250_regs.h>
+#include <mips/sibyte/dev/sbbuswatchvar.h>
+
+#define READ_REG(rp) (mips3_ld((volatile uint64_t *)(rp)))
+#define WRITE_REG(rp, val) (mips3_sd((volatile uint64_t *)(rp), (val)))
+
+static void sibyte_bus_watch_intr(void *, uint32_t, vaddr_t);
+
+void
+sibyte_bus_watch_init(void)
+{
+ (void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
+ WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
+ WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
+
+ (void)cpu_intr_establish(K_INT_BAD_ECC, IPL_DDB,
+ sibyte_bus_watch_intr, (void *)K_INT_BAD_ECC);
+ (void)cpu_intr_establish(K_INT_COR_ECC, IPL_DDB,
+ sibyte_bus_watch_intr, (void *)K_INT_COR_ECC);
+ (void)cpu_intr_establish(K_INT_IO_BUS, IPL_DDB,
+ sibyte_bus_watch_intr, (void *)K_INT_IO_BUS);
+}
+
+int
+sibyte_bus_watch_check(unsigned int cause)
+{
+ uint64_t err_ctl;
+ uint64_t cache_err_i;
+ uint64_t cache_err_d;
+ uint64_t cache_err_dpa;
+ uint64_t bus_err_dpa;
+ uint32_t bus_err_status;
+ uint32_t l2_errors;
+ uint32_t mem_io_errors;
+
+ bus_err_status = READ_REG(
+ MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
+
+ if (bus_err_status == 0)
+ return 0;
+
+ l2_errors = READ_REG(
+ MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS));
+ if (l2_errors != 0)
+ WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
+
+ mem_io_errors = READ_REG(
+ MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS));
+ if (mem_io_errors != 0)
+ WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
+
+ asm volatile("dmfc0 %0, $26, 0;" : "=r"(err_ctl));
+ asm volatile("dmfc0 %0, $26, 1;" : "=r"(bus_err_dpa));
+ asm volatile("dmfc0 %0, $27, 0;" : "=r"(cache_err_i));
+ asm volatile("dmfc0 %0, $27, 1;" : "=r"(cache_err_d));
+ asm volatile("dmfc0 %0, $27, 3;" : "=r"(cache_err_dpa));
+
+ printf("bus_err_status=%#x\n", bus_err_status);
+ printf("l2_errors=%#x\n", l2_errors);
+ printf("mem_io_errors=%#x\n", mem_io_errors);
+ printf("err_ctl=%#"PRIx64"\n", err_ctl);
+ printf("bus_err_dpa=%#"PRIx64"\n", bus_err_dpa);
+ printf("cache_err_i=%#"PRIx64"\n", cache_err_i);
+ printf("cache_err_d=%#"PRIx64"\n", cache_err_d);
+ printf("cache_err_dpa=%#"PRIx64"\n", cache_err_dpa);
+
+ return -1;
+}
+
+static void
+sibyte_bus_watch_intr(void *arg, uint32_t status, vaddr_t pc)
+{
+ printf("%s: %p\n", __func__, arg);
+ (void)sibyte_bus_watch_check(0);
+}
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbbuswatchvar.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/sibyte/dev/sbbuswatchvar.h Sun Feb 20 07:47:38 2011 +0000
@@ -0,0 +1,36 @@
+/* $NetBSD: sbbuswatchvar.h,v 1.2 2011/02/20 07:47:39 matt Exp $ */
+/*
+ * Copyright (c) 2010, The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Cliff Neighbors.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_SIBYTE_DEV_SBBUSWATCHVAR_H
+#define _ARCH_SIBYTE_DEV_SBBUSWATCHVAR_H
+
+extern void sibyte_bus_watch_init(void);
+extern int sibyte_bus_watch_check(unsigned int);
+
+#endif /* _ARCH_SIBYTE_DEV_SBBUSWATCHVAR_H */
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbmac.c
--- a/sys/arch/mips/sibyte/dev/sbmac.c Sun Feb 20 07:45:46 2011 +0000
+++ b/sys/arch/mips/sibyte/dev/sbmac.c Sun Feb 20 07:47:38 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbmac.c,v 1.39 2011/02/01 06:13:08 matt Exp $ */
+/* $NetBSD: sbmac.c,v 1.40 2011/02/20 07:47:39 matt Exp $ */
/*
* Copyright 2000, 2001, 2004
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sbmac.c,v 1.39 2011/02/01 06:13:08 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sbmac.c,v 1.40 2011/02/20 07:47:39 matt Exp $");
#include "opt_inet.h"
#include "opt_ns.h"
@@ -2273,7 +2273,7 @@
/* Determine controller base address */
- sc->sbm_base = sa->sa_locs.sa_addr;
+ sc->sbm_base = sa->sa_base + sa->sa_locs.sa_offset;
eaddr = sc->sbm_hwaddr;
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbobio.c
--- a/sys/arch/mips/sibyte/dev/sbobio.c Sun Feb 20 07:45:46 2011 +0000
+++ b/sys/arch/mips/sibyte/dev/sbobio.c Sun Feb 20 07:47:38 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbobio.c,v 1.20 2011/02/01 06:13:08 matt Exp $ */
+/* $NetBSD: sbobio.c,v 1.21 2011/02/20 07:47:39 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sbobio.c,v 1.20 2011/02/01 06:13:08 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sbobio.c,v 1.21 2011/02/20 07:47:39 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -236,7 +236,7 @@
memset(&sa, 0, sizeof sa);
sa.sa_locs = devs[i];
- locs[SBOBIOCF_ADDR] = devs[i].sa_addr;
+ locs[SBOBIOCF_OFFSET] = devs[i].sa_offset;
locs[SBOBIOCF_INTR + 0] = devs[i].sa_intr[0];
locs[SBOBIOCF_INTR + 1] = devs[i].sa_intr[1];
@@ -255,7 +255,7 @@
if (pnp)
aprint_normal("%s at %s",
sbobio_device_type_name(sap->sa_locs.sa_type), pnp);
- aprint_normal(" addr 0x%x", sap->sa_locs.sa_addr);
+ aprint_normal(" offset 0x%lx", sap->sa_locs.sa_offset);
for (i = 0; i < 2; i++) {
if (sap->sa_locs.sa_intr[i] != SBOBIOCF_INTR_DEFAULT)
aprint_normal("%s%d", i == 0 ? " intr " : ",",
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbobiovar.h
--- a/sys/arch/mips/sibyte/dev/sbobiovar.h Sun Feb 20 07:45:46 2011 +0000
+++ b/sys/arch/mips/sibyte/dev/sbobiovar.h Sun Feb 20 07:47:38 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbobiovar.h,v 1.3 2009/08/12 12:56:29 simonb Exp $ */
+/* $NetBSD: sbobiovar.h,v 1.4 2011/02/20 07:47:39 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -33,7 +33,7 @@
*/
/* sbobio pseudo-offset (from base) of an on-board device*/
-typedef u_int sbobio_offset;
+typedef u_long sbobio_offset;
/* type of an on-board device. Matches table in sbobio.c */
enum sbobio_device_type {
@@ -46,7 +46,7 @@
/* autoconfiguration match information for zbbus children */
struct sbobio_attach_locs {
- sbobio_offset sa_addr;
+ sbobio_offset sa_offset;
u_int sa_intr[2];
enum sbobio_device_type sa_type;
};
@@ -54,4 +54,6 @@
/* XXX can probably just get away without separate sbobio_attach_locs ? */
struct sbobio_attach_args {
struct sbobio_attach_locs sa_locs;
+
+ sbobio_offset sa_base;
};
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbscd.c
--- a/sys/arch/mips/sibyte/dev/sbscd.c Sun Feb 20 07:45:46 2011 +0000
+++ b/sys/arch/mips/sibyte/dev/sbscd.c Sun Feb 20 07:47:38 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbscd.c,v 1.17 2011/02/01 06:13:08 matt Exp $ */
+/* $NetBSD: sbscd.c,v 1.18 2011/02/20 07:47:39 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sbscd.c,v 1.17 2011/02/01 06:13:08 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sbscd.c,v 1.18 2011/02/20 07:47:39 matt Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -111,7 +111,7 @@
memset(&sa, 0, sizeof sa);
sa.sa_locs = sb1250_sbscd_devs[i];
- locs[SBSCDCF_ADDR] = sb1250_sbscd_devs[i].sa_addr;
+ locs[SBSCDCF_OFFSET] = sb1250_sbscd_devs[i].sa_offset;
locs[SBSCDCF_INTR + 0] =
sb1250_sbscd_devs[i].sa_intr[0];
locs[SBSCDCF_INTR + 1] =
@@ -132,7 +132,7 @@
if (pnp)
aprint_normal("%s at %s",
sbscd_device_type_name(sap->sa_locs.sa_type), pnp);
- aprint_normal(" addr 0x%x", sap->sa_locs.sa_addr);
+ aprint_normal(" offset 0x%lx", sap->sa_locs.sa_offset);
for (i = 0; i < 2; i++) {
if (sap->sa_locs.sa_intr[i] != -1)
aprint_normal("%s%d", i == 0 ? " intr " : ",",
diff -r 3aab344183bc -r 17af4568f0a5 sys/arch/mips/sibyte/dev/sbscdvar.h
--- a/sys/arch/mips/sibyte/dev/sbscdvar.h Sun Feb 20 07:45:46 2011 +0000
+++ b/sys/arch/mips/sibyte/dev/sbscdvar.h Sun Feb 20 07:47:38 2011 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbscdvar.h,v 1.3 2009/08/12 12:56:29 simonb Exp $ */
+/* $NetBSD: sbscdvar.h,v 1.4 2011/02/20 07:47:39 matt Exp $ */
/*
* Copyright 2000, 2001
@@ -33,7 +33,7 @@
*/
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