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[src/netbsd-2-0]: src/sys/arch/sparc64/sparc64 Apply patch (requested by mart...
details: https://anonhg.NetBSD.org/src/rev/36f35bb23a70
branches: netbsd-2-0
changeset: 564767:36f35bb23a70
user: tron <tron%NetBSD.org@localhost>
date: Sun May 01 11:23:38 2005 +0000
description:
Apply patch (requested by martin in ticket #1487):
Various changes from NetBSD-current, revisions 1.197 to 1.204.
Interrupt and soft-interrupt handling changes that appear to fix
the "sleep forever" problem (PR port-sparc64/21750).
diffstat:
sys/arch/sparc64/sparc64/locore.s | 495 +++++++------------------------------
1 files changed, 97 insertions(+), 398 deletions(-)
diffs (truncated from 881 to 300 lines):
diff -r 0649184bc087 -r 36f35bb23a70 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Fri Apr 22 07:00:49 2005 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Sun May 01 11:23:38 2005 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.196.2.1 2004/07/25 07:45:01 tron Exp $ */
+/* $NetBSD: locore.s,v 1.196.2.2 2005/05/01 11:23:38 tron Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -54,10 +54,8 @@
*
* @(#)locore.s 8.4 (Berkeley) 12/10/93
*/
-#define INTRLIST
#define SPITFIRE /* We don't support Cheetah (USIII) yet */
-#define INTR_INTERLOCK /* Use IH_PEND field to interlock interrupts */
#undef PARANOID /* Extremely expensive consistency checks */
#undef NO_VCACHE /* Map w/D$ disabled */
#ifdef DEBUG
@@ -67,12 +65,8 @@
#undef TRAPSTATS /* Count traps */
#undef TRAPS_USE_IG /* Use Interrupt Globals for all traps */
#define HWREF /* Track ref/mod bits in trap handlers */
-#undef PMAP_FPSTATE /* Allow nesting of VIS pmap copy/zero */
-#define NEW_FPSTATE
-#define PMAP_PHYS_PAGE /* Use phys ASIs for pmap copy/zero */
#undef DCACHE_BUG /* Flush D$ around ASI_PHYS accesses */
#undef NO_TSB /* Don't use TSB */
-#define TICK_IS_TIME /* Keep %tick synchronized with time */
#undef SCHED_DEBUG
#include "opt_ddb.h"
@@ -429,13 +423,6 @@
#endif
/*
- * _cpcb points to the current pcb (and hence u. area).
- * Initially this is the special one.
- */
- .globl _C_LABEL(cpcb)
-_C_LABEL(cpcb): POINTER _C_LABEL(u0)
-
-/*
* romp is the prom entry pointer
* romtba is the prom trap table base address
*/
@@ -445,44 +432,6 @@
romtba: POINTER 0
-/* NB: Do we really need the following around? */
-/*
- * _cputyp is the current CPU type, used to distinguish between
- * the many variations of different sun4* machines. It contains
- * the value CPU_SUN4, CPU_SUN4C, or CPU_SUN4M.
- */
- .globl _C_LABEL(cputyp)
-_C_LABEL(cputyp):
- .word 1
-/*
- * _cpumod is the current CPU model, used to distinguish between variants
- * in the Sun4 and Sun4M families. See /sys/arch/sparc64/include/param.h
- * for possible values.
- */
- .globl _C_LABEL(cpumod)
-_C_LABEL(cpumod):
- .word 1
-/*
- * _mmumod is the current mmu model, used to distinguish between the
- * various implementations of the SRMMU in the sun4m family of machines.
- * See /sys/arch/sparc64/include/param.h for possible values.
- */
- .globl _C_LABEL(mmumod)
-_C_LABEL(mmumod):
- .word 0
-
-/*
- * There variables are pointed to by the cpp symbols PGSHIFT, NBPG,
- * and PGOFSET.
- */
- .globl _C_LABEL(pgshift), _C_LABEL(nbpg), _C_LABEL(pgofset)
-_C_LABEL(pgshift):
- .word 0
-_C_LABEL(nbpg):
- .word 0
-_C_LABEL(pgofset):
- .word 0
-
_ALIGN
.text
@@ -907,33 +856,33 @@
UTRAP(T_ECCERR) ! We'll implement this one later
ufast_IMMU_miss: ! 064 = fast instr access MMU miss
TRACEFLT ! DEBUG
- ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
+ ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
#ifdef NO_TSB
- ba,a %icc, instr_miss;
-#endif
- ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
- ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 !Load TSB tag:data into %g4:%g5
- brgez,pn %g5, instr_miss ! Entry invalid? Punt
- cmp %g1, %g4 ! Compare TLB tags
- bne,pn %xcc, instr_miss ! Got right tag?
+ ba,a %icc, instr_miss
+#endif
+ ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
+ ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag:data into %g4:%g5
+ brgez,pn %g5, instr_miss ! Entry invalid? Punt
+ cmp %g1, %g4 ! Compare TLB tags
+ bne,pn %xcc, instr_miss ! Got right tag?
nop
CLRTT
- stxa %g5, [%g0] ASI_IMMU_DATA_IN! Enter new mapping
- retry ! Try new mapping
+ stxa %g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
+ retry ! Try new mapping
1:
sir
TA32
ufast_DMMU_miss: ! 068 = fast data access MMU miss
TRACEFLT ! DEBUG
- ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
+ ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
#ifdef NO_TSB
- ba,a %icc, data_miss;
-#endif
- ldxa [%g0] ASI_DMMU, %g1 ! Hard coded for unified 8K TSB Load DMMU tag target register
- ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
- brgez,pn %g5, data_miss ! Entry invalid? Punt
- cmp %g1, %g4 ! Compare TLB tags
- bnz,pn %xcc, data_miss ! Got right tag?
+ ba,a %icc, data_miss
+#endif
+ ldxa [%g0] ASI_DMMU, %g1 ! Load DMMU tag target register
+ ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
+ brgez,pn %g5, data_miss ! Entry invalid? Punt
+ cmp %g1, %g4 ! Compare TLB tags
+ bnz,pn %xcc, data_miss ! Got right tag?
nop
CLRTT
#ifdef TRAPSTATS
@@ -942,8 +891,8 @@
inc %g2
stw %g2, [%g1+%lo(_C_LABEL(udhit))]
#endif
- stxa %g5, [%g0] ASI_DMMU_DATA_IN! Enter new mapping
- retry ! Try new mapping
+ stxa %g5, [%g0] ASI_DMMU_DATA_IN ! Enter new mapping
+ retry ! Try new mapping
1:
sir
TA32
@@ -1150,33 +1099,33 @@
UTRAP(T_ECCERR) ! We'll implement this one later
kfast_IMMU_miss: ! 064 = fast instr access MMU miss
TRACEFLT ! DEBUG
- ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
+ ldxa [%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
#ifdef NO_TSB
- ba,a %icc, instr_miss;
-#endif
- ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
- ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 !Load TSB tag:data into %g4:%g5
- brgez,pn %g5, instr_miss ! Entry invalid? Punt
- cmp %g1, %g4 ! Compare TLB tags
- bne,pn %xcc, instr_miss ! Got right tag?
+ ba,a %icc, instr_miss
+#endif
+ ldxa [%g0] ASI_IMMU, %g1 ! Load IMMU tag target register
+ ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag:data into %g4:%g5
+ brgez,pn %g5, instr_miss ! Entry invalid? Punt
+ cmp %g1, %g4 ! Compare TLB tags
+ bne,pn %xcc, instr_miss ! Got right tag?
nop
CLRTT
- stxa %g5, [%g0] ASI_IMMU_DATA_IN! Enter new mapping
- retry ! Try new mapping
+ stxa %g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
+ retry ! Try new mapping
1:
sir
TA32
kfast_DMMU_miss: ! 068 = fast data access MMU miss
TRACEFLT ! DEBUG
- ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
+ ldxa [%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
#ifdef NO_TSB
- ba,a %icc, data_miss;
-#endif
- ldxa [%g0] ASI_DMMU, %g1 ! Hard coded for unified 8K TSB Load DMMU tag target register
- ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
- brgez,pn %g5, data_miss ! Entry invalid? Punt
- cmp %g1, %g4 ! Compare TLB tags
- bnz,pn %xcc, data_miss ! Got right tag?
+ ba,a %icc, data_miss
+#endif
+ ldxa [%g0] ASI_DMMU, %g1 ! Load DMMU tag target register
+ ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB tag and data into %g4 and %g5
+ brgez,pn %g5, data_miss ! Entry invalid? Punt
+ cmp %g1, %g4 ! Compare TLB tags
+ bnz,pn %xcc, data_miss ! Got right tag?
nop
CLRTT
#ifdef TRAPSTATS
@@ -1185,8 +1134,8 @@
inc %g2
stw %g2, [%g1+%lo(_C_LABEL(kdhit))]
#endif
- stxa %g5, [%g0] ASI_DMMU_DATA_IN! Enter new mapping
- retry ! Try new mapping
+ stxa %g5, [%g0] ASI_DMMU_DATA_IN ! Enter new mapping
+ retry ! Try new mapping
1:
sir
TA32
@@ -2144,8 +2093,8 @@
and %g6, PTMASK, %g6
add %g5, %g4, %g5
brz,pn %g4, winfix ! NULL entry? check somewhere else
-
nop
+
ldxa [%g5] ASI_PHYS_CACHED, %g4
sll %g6, 3, %g6
brz,pn %g4, winfix ! NULL entry? check somewhere else
@@ -2175,9 +2124,8 @@
ldxa [%g0] ASI_DMMU_8KPTR, %g2 ! Load DMMU 8K TSB pointer
andcc %g5, 0x3, %g5 ! 8K?
bnz,pn %icc, winfix ! We punt to the pmap code since we can't handle policy
- ldxa [%g0] ASI_DMMU, %g1 ! Hard coded for unified 8K TSB Load DMMU tag target register
+ ldxa [%g0] ASI_DMMU, %g1 ! Load DMMU tag target register
casxa [%g6] ASI_PHYS_CACHED, %g4, %g7 ! and write it out
-
membar #StoreLoad
cmp %g4, %g7
bne,pn %xcc, 1b
@@ -2186,6 +2134,7 @@
mov SFSR, %g7
stx %g4, [%g2+8] ! Update TSB entry data
nop
+
#ifdef DEBUG
set DATA_START, %g6 ! debug
stx %g1, [%g6+0x40] ! debug
@@ -3808,8 +3757,7 @@
* int type;
* struct trapframe *tf0;
*/
- .globl _C_LABEL(kgdb_trap_glue)
-_C_LABEL(kgdb_trap_glue):
+ENTRY_NOPROFILE(kgdb_trap_glue)
save %sp, -CCFSZ, %sp
flushw ! flush all windows
@@ -4019,9 +3967,6 @@
* shift instead of multiply for address calculation). It hunts for
* any available slot at that level. Available slots are NULL.
*
- * NOTE: If no slots are available, we issue an un-vectored interrupt,
- * but it will probably be lost anyway.
- *
* Then interrupt_vector uses the interrupt level in the intrhand
* to issue a softint of the appropriate level. The softint handler
* figures out what level interrupt it's handling and pulls the first
@@ -4124,18 +4069,14 @@
nop
setup_sparcintr:
-#ifdef INTR_INTERLOCK
LDPTR [%g5+IH_PEND], %g6 ! Read pending flag
brnz,pn %g6, ret_from_intr_vector ! Skip it if it's running
-#endif
ldub [%g5+IH_PIL], %g6 ! Read interrupt mask
sethi %hi(intrpending), %g1
- mov 8, %g7 ! Number of slots to search
sll %g6, PTRSHFT+3, %g3 ! Find start of table for this IPL
or %g1, %lo(intrpending), %g1
add %g1, %g3, %g1
1:
-#ifdef INTRLIST
LDPTR [%g1], %g3 ! Load list head
STPTR %g3, [%g5+IH_PEND] ! Link our intrhand node in
mov %g5, %g7
@@ -4143,52 +4084,6 @@
cmp %g7, %g3 ! Did it work?
bne,pn %xcc, 1b ! No, try again
nop
-#else /* INTRLIST */
- mov %g5, %g3
- CASPTR [%g1] ASI_N, %g0, %g3 ! Try a slot -- MPU safe
- brz,pt %g3, 2f ! Available?
-#ifdef DEBUG
- cmp %g5, %g3 ! if these are the same
- bne,pt %icc, 97f ! then we aleady have the
- nop ! interrupt registered
- set _C_LABEL(intrdebug), %g4
- ld [%g4], %g4
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