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[src/netbsd-1-6]: src/sys/arch/arm/arm Pull up revision 1.7 (requested by tho...



details:   https://anonhg.NetBSD.org/src/rev/5b137b9f1aa3
branches:  netbsd-1-6
changeset: 529409:5b137b9f1aa3
user:      he <he%NetBSD.org@localhost>
date:      Mon Nov 18 02:41:45 2002 +0000

description:
Pull up revision 1.7 (requested by thorpej in ticket #690):
  Convert bpl's to bhi's, saves looping more than needed in
  some cases.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_sa1.S |  10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (45 lines):

diff -r 2055e6aa8428 -r 5b137b9f1aa3 sys/arch/arm/arm/cpufunc_asm_sa1.S
--- a/sys/arch/arm/arm/cpufunc_asm_sa1.S        Mon Nov 18 02:37:47 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_sa1.S        Mon Nov 18 02:41:45 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_sa1.S,v 1.5 2002/05/03 16:45:22 rjs Exp $  */
+/*     $NetBSD: cpufunc_asm_sa1.S,v 1.5.4.1 2002/11/18 02:41:45 he Exp $       */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -224,7 +224,7 @@
 1:     mcr     p15, 0, r0, c7, c10, 1  /* clean D cache entry */
        add     r0, r0, #32
        subs    r1, r1, #32
-       bpl     1b
+       bhi     1b
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        mov     pc, lr
@@ -241,7 +241,7 @@
        mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
        add     r0, r0, #32
        subs    r1, r1, #32
-       bpl     1b
+       bhi     1b
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        mcr     p15, 0, r0, c7, c5, 0   /* flush I cache */
@@ -259,7 +259,7 @@
        mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
        add     r0, r0, #32
        subs    r1, r1, #32
-       bpl     1b
+       bhi     1b
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        mov     pc, lr
@@ -275,7 +275,7 @@
 1:     mcr     p15, 0, r0, c7, c10, 1  /* clean D cache entry */
        add     r0, r0, #32
        subs    r1, r1, #32
-       bpl     1b
+       bhi     1b
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        mcr     p15, 0, r0, c7, c5, 0   /* flush I cache */



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