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[src/trunk]: src/sys/arch/sparc/sparc GC the per-CPU message lock.



details:   https://anonhg.NetBSD.org/src/rev/4b8858144803
branches:  trunk
changeset: 542201:4b8858144803
user:      pk <pk%NetBSD.org@localhost>
date:      Thu Jan 23 18:49:08 2003 +0000

description:
GC the per-CPU message lock.
Move the level 15 msg area further down the cpuinfo structure, as it's
used infrequently.

diffstat:

 sys/arch/sparc/sparc/cpuvar.h |  19 ++++++++-----------
 1 files changed, 8 insertions(+), 11 deletions(-)

diffs (55 lines):

diff -r afa88e4018b8 -r 4b8858144803 sys/arch/sparc/sparc/cpuvar.h
--- a/sys/arch/sparc/sparc/cpuvar.h     Thu Jan 23 18:32:07 2003 +0000
+++ b/sys/arch/sparc/sparc/cpuvar.h     Thu Jan 23 18:49:08 2003 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpuvar.h,v 1.55 2003/01/20 20:51:34 pk Exp $ */
+/*     $NetBSD: cpuvar.h,v 1.56 2003/01/23 18:49:08 pk Exp $ */
 
 /*
  *  Copyright (c) 1996 The NetBSD Foundation, Inc.
@@ -89,9 +89,9 @@
 };
 
 struct xpmsg {
-       struct simplelock       lock;
        __volatile int tag;
-#define        XPMSG_FUNC                      4
+#define        XPMSG15_PAUSECPU        1
+#define        XPMSG_FUNC              4
 
        __volatile union {
                struct xpmsg_func {
@@ -105,11 +105,6 @@
        } u;
 };
 
-struct xpmsg_lev15 {
-       __volatile int tag;
-#define        XPMSG15_PAUSECPU                1
-};
-
 /*
  * This must be locked around all message transactions to ensure only
  * one CPU is generating them.
@@ -145,9 +140,8 @@
         */
        struct cpu_info * __volatile ci_self;
 
-       /* Inter-processor message areas */
-       struct xpmsg msg;
-       struct xpmsg_lev15 msg_lev15;
+       /* Primary Inter-processor message area */
+       struct xpmsg    msg;
 
        int             ci_cpuid;       /* CPU index (see cpus[] array) */
 
@@ -248,6 +242,9 @@
 
        int     cpu_type;       /* Type: see CPUTYP_xxx below */
 
+       /* Inter-processor message area (high priority but used infrequently) */
+       struct xpmsg    msg_lev15;
+
        /* CPU information */
        int             node;           /* PROM node for this CPU */
        int             mid;            /* Module ID for MP systems */



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