[src/trunk]: src/sys/arch/arm/include Add bits for the XScale Auxillary Contr...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7c231d6c4e4d
branches:  trunk
changeset: 525695:7c231d6c4e4d
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Mon Apr 15 16:34:32 2002 +0000

description:
Add bits for the XScale Auxillary Control Register.

diffstat:

 sys/arch/arm/include/armreg.h |  9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diffs (23 lines):

diff -r 1ac1f2a2ad2c -r 7c231d6c4e4d sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Mon Apr 15 15:05:58 2002 +0000
+++ b/sys/arch/arm/include/armreg.h     Mon Apr 15 16:34:32 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.15 2002/04/03 22:12:52 thorpej Exp $      */
+/*     $NetBSD: armreg.h,v 1.16 2002/04/15 16:34:32 thorpej Exp $      */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -260,6 +260,13 @@
 
 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
 
+/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
+#define        XSCALE_AUXCTL_K         0x00000001 /* dis. write buffer coalescing */
+#define        XSCALE_AUXCTL_P         0x00000002 /* ECC protect page table access */
+#define        XSCALE_AUXCTL_MD_WB_RA  0x00000000 /* mini-D$ wb, read-allocate */
+#define        XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
+#define        XSCALE_AUXCTL_MB_WT     0x00000020 /* mini-D$ wt, read-allocate */
+
 /* Cache type register definitions */
 #define        CPU_CT_ISIZE(x)         ((x) & 0xfff)           /* I$ info */
 #define        CPU_CT_DSIZE(x)         (((x) >> 12) & 0xfff)   /* D$ info */