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[src/trunk]: src/sys/arch/mips Add option to apply additional mask to the SR ...
details: https://anonhg.NetBSD.org/src/rev/039c78304401
branches: trunk
changeset: 495279:039c78304401
user: jeffs <jeffs%NetBSD.org@localhost>
date: Tue Jul 25 17:56:05 2000 +0000
description:
Add option to apply additional mask to the SR at run-time for MIPS3 platforms.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.
diffstat:
sys/arch/mips/include/asm.h | 20 +++++++++++++++++++-
sys/arch/mips/mips/locore.S | 15 ++++++++++++++-
sys/arch/mips/mips/locore_mips3.S | 30 ++++++++++++++++++------------
3 files changed, 51 insertions(+), 14 deletions(-)
diffs (241 lines):
diff -r db70d873c3a5 -r 039c78304401 sys/arch/mips/include/asm.h
--- a/sys/arch/mips/include/asm.h Tue Jul 25 17:26:36 2000 +0000
+++ b/sys/arch/mips/include/asm.h Tue Jul 25 17:56:05 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.24 2000/06/23 12:18:48 kleink Exp $ */
+/* $NetBSD: asm.h,v 1.25 2000/07/25 17:56:05 jeffs Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -293,4 +293,22 @@
#define SZREG 8
#endif /* _MIPS_BSD_API */
+/*
+ * The DYNAMIC_STATUS_MASK option adds an additional masking operation
+ * when updating the hardware interrupt mask in the status register.
+ *
+ * This is useful for platforms that need to at run-time mask
+ * interrupts based on motherboard configuration or to handle
+ * slowly clearing interrupts.
+ *
+ * XXX this is only currently implemented for mips3.
+ */
+#ifdef MIPS_DYNAMIC_STATUS_MASK
+#define DYNAMIC_STATUS_MASK(sr,scratch) \
+ lw scratch, mips_dynamic_status_mask; \
+ and sr, sr, scratch
+#else
+#define DYNAMIC_STATUS_MASK(sr,scratch)
+#endif
+
#endif /* _MIPS_ASM_H */
diff -r db70d873c3a5 -r 039c78304401 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S Tue Jul 25 17:26:36 2000 +0000
+++ b/sys/arch/mips/mips/locore.S Tue Jul 25 17:56:05 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.110 2000/07/20 18:33:42 jeffs Exp $ */
+/* $NetBSD: locore.S,v 1.111 2000/07/25 17:56:05 jeffs Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -279,6 +279,7 @@
*/
LEAF(mips_idle)
li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ DYNAMIC_STATUS_MASK(t0,t1) # machine dependent masking
mtc0 t0, MIPS_COP_0_STATUS # enable all interrupts
nop
sw zero, _C_LABEL(curproc) # set curproc NULL for stats
@@ -414,6 +415,7 @@
REG_PROLOGUE
REG_L v0, U_PCB_CONTEXT+SF_REG_SR(a0)
+ DYNAMIC_STATUS_MASK(v0,ra) # machine dependent masking
REG_L ra, U_PCB_CONTEXT+SF_REG_RA(a0)
REG_L s0, U_PCB_CONTEXT+SF_REG_S0(a0)
REG_L s1, U_PCB_CONTEXT+SF_REG_S1(a0)
@@ -501,6 +503,7 @@
LEAF(longjmp)
REG_PROLOGUE
REG_L v0, SF_REG_SR(a0)
+ DYNAMIC_STATUS_MASK(v0,ra) # machine dependent masking
REG_L ra, SF_REG_RA(a0)
REG_L s0, SF_REG_S0(a0)
REG_L s1, SF_REG_S1(a0)
@@ -531,6 +534,7 @@
and a0, a0, MIPS_INT_MASK # extract INT bits
nor a0, zero, a0 # bitwise inverse of A0
and a0, a0, v0 # disable retaining other bits
+ DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
mtc0 a0, MIPS_COP_0_STATUS # store back
nop
j ra
@@ -544,6 +548,7 @@
nor a0, zero, a0 # bitwise inverse of A0
and a0, a0, MIPS_INT_MASK # extract INT bits
or a0, a0, v1 # disable making other bits on
+ DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
mtc0 a0, MIPS_COP_0_STATUS # store back
nop
j ra
@@ -556,6 +561,7 @@
li v1, ~MIPS_INT_MASK
and v1, v1, v0 # turn off every INT bit
or v1, v1, a0 # set old INT bits
+ DYNAMIC_STATUS_MASK(v1,t0) # machine dependent masking
mtc0 v1, MIPS_COP_0_STATUS # store back
nop
j ra
@@ -569,6 +575,7 @@
li v1, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
and v1, v1, v0 # turn off every INT bit
or v1, v1, a0 # set old INT bits
+ DYNAMIC_STATUS_MASK(v1,t0) # machine dependent masking
mtc0 v1, MIPS_COP_0_STATUS # store back
nop
j ra
@@ -613,6 +620,7 @@
LEAF(_splnone)
mtc0 zero, MIPS_COP_0_CAUSE # clear SOFT_INT bits
li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+ DYNAMIC_STATUS_MASK(v0,t0) # machine dependent masking
mtc0 v0, MIPS_COP_0_STATUS # enable all sources
nop
j ra
@@ -1319,3 +1327,8 @@
.word 0
_C_LABEL(mips_L2CachePresent):
.word 0
+#ifdef MIPS_DYNAMIC_STATUS_MASK
+ .globl _C_LABEL(mips_dynamic_status_mask)
+_C_LABEL(mips_dynamic_status_mask):
+ .word 0xffffffff
+#endif
diff -r db70d873c3a5 -r 039c78304401 sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Tue Jul 25 17:26:36 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Tue Jul 25 17:56:05 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.41 2000/07/20 18:14:47 jeffs Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.42 2000/07/25 17:56:06 jeffs Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -626,10 +626,11 @@
REG_L s7, FRAME_S7(k1)
REG_L t8, FRAME_T8(k1)
REG_L t9, FRAME_T9(k1)
+ REG_L k0, FRAME_SR(k1)
+ DYNAMIC_STATUS_MASK(k0,ra) # machine dependent masking
REG_L gp, FRAME_GP(k1)
REG_L sp, FRAME_SP(k1)
REG_L s8, FRAME_S8(k1)
- REG_L k0, FRAME_SR(k1)
REG_L ra, FRAME_RA(k1)
mtc0 k0, MIPS_COP_0_STATUS # restore status
nop
@@ -760,10 +761,11 @@
REG_L s7, FRAME_S7(k1)
REG_L t8, FRAME_T8(k1)
REG_L t9, FRAME_T9(k1)
+ REG_L k0, FRAME_SR(k1)
+ DYNAMIC_STATUS_MASK(k0,ra) # machine dependent masking
REG_L gp, FRAME_GP(k1)
REG_L sp, FRAME_SP(k1)
REG_L s8, FRAME_S8(k1)
- REG_L k0, FRAME_SR(k1)
REG_L ra, FRAME_RA(k1)
mtc0 k0, MIPS_COP_0_STATUS
nop # 3 nops before eret
@@ -835,6 +837,7 @@
nop
nop
REG_L a0, TF_BASE+TF_REG_SR(sp) # ??? why differs ???
+ DYNAMIC_STATUS_MASK(a0,t0) # machine dependent masking
REG_L t0, TF_BASE+TF_REG_MULLO(sp)
REG_L t1, TF_BASE+TF_REG_MULHI(sp)
REG_L v0, TF_BASE+TF_REG_EPC(sp)
@@ -982,6 +985,7 @@
REG_L a0, FRAME_EPC(a1) # argument is interrupted PC
li t0, MIPS_HARD_INT_MASK | MIPS_SR_INT_IE
+ DYNAMIC_STATUS_MASK(t0,t1) # machine dependent masking
jal _C_LABEL(ast)
mtc0 t0, MIPS_COP_0_STATUS # enable interrupts (spl0)
@@ -1039,12 +1043,13 @@
REG_L t7, FRAME_T7(k1)
REG_L t8, FRAME_T8(k1)
REG_L t9, FRAME_T9(k1)
+ REG_L k0, FRAME_SR(k1)
+ DYNAMIC_STATUS_MASK(k0,ra) # machine dependent masking
REG_L gp, FRAME_GP(k1)
REG_L sp, FRAME_SP(k1)
- REG_L k0, FRAME_SR(k1)
REG_L ra, FRAME_RA(k1)
mtc0 k0, MIPS_COP_0_STATUS # restore the SR
- nop # Required for QED 5230
+ nop # required for QED 5230
nop
eret # return to interrupted point
.set at
@@ -1099,7 +1104,7 @@
addu k1, k1, k0
tlbp # Probe the invalid entry
and k0, k0, 4 # check even/odd page
- nop # Required for QED 5230
+ nop # required for QED 5230
bne k0, zero, KernTLBIOdd
nop
@@ -1112,7 +1117,7 @@
dsrl k0, k0, 34
dmtc0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
and k0, k0, MIPS3_PG_V # check for valid entry
- nop # Required for QED5230
+ nop # required for QED5230
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
lw k0, 4(k1) # get odd PTE entry
dsll k0, k0, 34
@@ -1122,7 +1127,7 @@
or k1, k1, k0
dmtc0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
nop
- nop # Required for QED5230
+ nop # required for QED5230
tlbwi # write TLB
nop
nop
@@ -1141,7 +1146,7 @@
dsrl k0, k0, 34
dmtc0 k0, MIPS_COP_0_TLB_LO1 # save PTE entry
and k0, k0, MIPS3_PG_V # check for valid entry
- nop # Required for QED5230
+ nop # required for QED5230
beq k0, zero, _C_LABEL(mips3_KernGenException) # PTE invalid
lw k0, -4(k1) # get even PTE entry
dsll k0, k0, 34
@@ -1281,8 +1286,8 @@
*/
LEAF(mips3_SetWIRED)
mtc0 a0, MIPS_COP_0_TLB_WIRED
- nop # Required for 5230
- nop # Required for 5230
+ nop # required for 5230
+ nop # required for 5230
j ra
nop
END(mips3_SetWIRED)
@@ -2153,10 +2158,11 @@
REG_L s7, FRAME_S7(k1)
REG_L t8, FRAME_T8(k1)
REG_L t9, FRAME_T9(k1)
+ REG_L k0, FRAME_SR(k1)
+ DYNAMIC_STATUS_MASK(k0,sp) # machine dependent masking
REG_L gp, FRAME_GP(k1)
REG_L s8, FRAME_S8(k1)
REG_L ra, FRAME_RA(k1)
- REG_L k0, FRAME_SR(k1)
REG_L sp, FRAME_SP(k1)
mtc0 k0, MIPS_COP_0_STATUS
nop
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