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[src/nathanw_sa]: src/sys/arch/macppc/dev Add/change prototypes so that macpc...
details: https://anonhg.NetBSD.org/src/rev/4372af4d2175
branches: nathanw_sa
changeset: 504785:4372af4d2175
user: simonb <simonb%NetBSD.org@localhost>
date: Tue Jun 19 12:02:57 2001 +0000
description:
Add/change prototypes so that macpcc builds with -Wstrict-prototypes.
diffstat:
sys/arch/macppc/dev/dbdma.h | 218 ++++++++++++++++++++++++++++++++++++
sys/arch/macppc/dev/viareg.h | 256 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 474 insertions(+), 0 deletions(-)
diffs (truncated from 482 to 300 lines):
diff -r 015e6f9aed6e -r 4372af4d2175 sys/arch/macppc/dev/dbdma.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/macppc/dev/dbdma.h Tue Jun 19 12:02:57 2001 +0000
@@ -0,0 +1,218 @@
+/* $NetBSD: dbdma.h,v 1.3.8.2 2001/06/19 12:02:57 simonb Exp $ */
+
+/*
+ * Copyright 1991-1998 by Open Software Foundation, Inc.
+ * All Rights Reserved
+ *
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies and
+ * that both the copyright notice and this permission notice appear in
+ * supporting documentation.
+ *
+ * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+ * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
+ * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
+ * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef _POWERMAC_DBDMA_H_
+#define _POWERMAC_DBDMA_H_
+
+#define DBDMA_CMD_OUT_MORE 0
+#define DBDMA_CMD_OUT_LAST 1
+#define DBDMA_CMD_IN_MORE 2
+#define DBDMA_CMD_IN_LAST 3
+#define DBDMA_CMD_STORE_QUAD 4
+#define DBDMA_CMD_LOAD_QUAD 5
+#define DBDMA_CMD_NOP 6
+#define DBDMA_CMD_STOP 7
+
+/* Keys */
+
+#define DBDMA_KEY_STREAM0 0
+#define DBDMA_KEY_STREAM1 1
+#define DBDMA_KEY_STREAM2 2
+#define DBDMA_KEY_STREAM3 3
+
+/* value 4 is reserved */
+#define DBDMA_KEY_REGS 5
+#define DBDMA_KEY_SYSTEM 6
+#define DBDMA_KEY_DEVICE 7
+
+#define DBDMA_INT_NEVER 0
+#define DBDMA_INT_IF_TRUE 1
+#define DBDMA_INT_IF_FALSE 2
+#define DBDMA_INT_ALWAYS 3
+
+#define DBDMA_BRANCH_NEVER 0
+#define DBDMA_BRANCH_IF_TRUE 1
+#define DBDMA_BRANCH_IF_FALSE 2
+#define DBDMA_BRANCH_ALWAYS 3
+
+#define DBDMA_WAIT_NEVER 0
+#define DBDMA_WAIT_IF_TRUE 1
+#define DBDMA_WAIT_IF_FALSE 2
+#define DBDMA_WAIT_ALWAYS 3
+
+
+/* Channels */
+
+#define DBDMA_SCSI0 0x0
+#define DBDMA_CURIO_SCSI DBDMA_SCSI0
+#define DBDMA_FLOPPY 0x1
+#define DBDMA_ETHERNET_TX 0x2
+#define DBDMA_ETHERNET_RV 0x3
+#define DBDMA_SCC_XMIT_A 0x4
+#define DBDMA_SCC_RECV_A 0x5
+#define DBDMA_SCC_XMIT_B 0x6
+#define DBDMA_SCC_RECV_B 0x7
+#define DBDMA_AUDIO_OUT 0x8
+#define DBDMA_AUDIO_IN 0x9
+#define DBDMA_SCSI1 0xA
+
+/* Control register values (in little endian) */
+
+#define DBDMA_STATUS_MASK 0x000000ff /* Status Mask */
+#define DBDMA_CNTRL_BRANCH 0x00000100
+ /* 0x200 reserved */
+#define DBDMA_CNTRL_ACTIVE 0x00000400
+#define DBDMA_CNTRL_DEAD 0x00000800
+#define DBDMA_CNTRL_WAKE 0x00001000
+#define DBDMA_CNTRL_FLUSH 0x00002000
+#define DBDMA_CNTRL_PAUSE 0x00004000
+#define DBDMA_CNTRL_RUN 0x00008000
+
+#define DBDMA_SET_CNTRL(x) ( ((x) | (x) << 16) )
+#define DBDMA_CLEAR_CNTRL(x) ( (x) << 16)
+
+
+#define DBDMA_REGMAP(channel) \
+ (dbdma_regmap_t *)((v_u_char *) POWERMAC_IO(PCI_DMA_BASE_PHYS) \
+ + (channel << 8))
+
+/* This struct is layout in little endian format */
+
+struct dbdma_command {
+ u_int16_t d_count;
+ u_int16_t d_command;
+ u_int32_t d_address;
+ u_int32_t d_cmddep;
+ u_int16_t d_resid;
+ u_int16_t d_status;
+};
+
+typedef struct dbdma_command dbdma_command_t;
+
+#define DBDMA_BUILD_CMD(d, cmd, key, interrupt, wait, branch) { \
+ dbdma_st16(&(d)->d_command, \
+ ((cmd) << 12) | ((key) << 8) | \
+ ((interrupt) << 4) | \
+ ((branch) << 2) | (wait)); \
+ }
+
+#define DBDMA_BUILD(d, cmd, key, count, address, interrupt, wait, branch) { \
+ dbdma_st16(&(d)->d_count, count); \
+ dbdma_st32(&(d)->d_address, address); \
+ (d)->d_resid = 0; \
+ (d)->d_status = 0; \
+ (d)->d_cmddep = 0; \
+ dbdma_st16(&(d)->d_command, \
+ ((cmd) << 12) | ((key) << 8) | \
+ ((interrupt) << 4) | \
+ ((branch) << 2) | (wait)); \
+ }
+
+static __inline__ void dbdma_st32(volatile u_int32_t *, u_int32_t);
+static __inline__ void dbdma_st16(volatile u_int16_t *, u_int16_t);
+static __inline__ u_int32_t dbdma_ld32(volatile u_int32_t *);
+static __inline__ u_int16_t dbdma_ld16(volatile u_int16_t *);
+
+static __inline__ void
+dbdma_st32(a, x)
+ volatile u_int32_t *a;
+ u_int32_t x;
+{
+ __asm__ volatile
+ ("stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
+}
+
+static __inline__ void
+dbdma_st16(a, x)
+ volatile u_int16_t *a;
+ u_int16_t x;
+{
+ __asm__ volatile
+ ("sthbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
+}
+
+static __inline__ u_int32_t
+dbdma_ld32(a)
+ volatile u_int32_t *a;
+{
+ u_int32_t swap;
+
+ __asm__ volatile
+ ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
+
+ return swap;
+}
+
+static __inline__ u_int16_t
+dbdma_ld16(a)
+ volatile u_int16_t *a;
+{
+ u_int16_t swap;
+
+ __asm__ volatile
+ ("lhbrx %0,0,%1" : "=r" (swap) : "r" (a));
+
+ return swap;
+}
+
+#define DBDMA_LD4_ENDIAN(a) dbdma_ld32(a)
+#define DBDMA_ST4_ENDIAN(a, x) dbdma_st32(a, x)
+
+/*
+ * DBDMA Channel layout
+ *
+ * NOTE - This structure is in little-endian format.
+ */
+
+struct dbdma_regmap {
+ u_int32_t d_control; /* Control Register */
+ u_int32_t d_status; /* DBDMA Status Register */
+ u_int32_t d_cmdptrhi; /* MSB of command pointer (not used yet) */
+ u_int32_t d_cmdptrlo; /* LSB of command pointer */
+ u_int32_t d_intselect; /* Interrupt Select */
+ u_int32_t d_branch; /* Branch selection */
+ u_int32_t d_wait; /* Wait selection */
+ u_int32_t d_transmode; /* Transfer modes */
+ u_int32_t d_dataptrhi; /* MSB of Data Pointer */
+ u_int32_t d_dataptrlo; /* LSB of Data Pointer */
+ u_int32_t d_reserved; /* Reserved for the moment */
+ u_int32_t d_branchptrhi; /* MSB of Branch Pointer */
+ u_int32_t d_branchptrlo; /* LSB of Branch Pointer */
+ /* The remaining fields are undefinied and unimplemented */
+};
+
+typedef volatile struct dbdma_regmap dbdma_regmap_t;
+
+/* DBDMA routines */
+
+void dbdma_start(dbdma_regmap_t *channel, dbdma_command_t *commands);
+void dbdma_stop(dbdma_regmap_t *channel);
+void dbdma_flush(dbdma_regmap_t *channel);
+void dbdma_reset(dbdma_regmap_t *channel);
+void dbdma_continue(dbdma_regmap_t *channel);
+void dbdma_pause(dbdma_regmap_t *channel);
+
+dbdma_command_t *dbdma_alloc(int); /* Allocate command structures */
+
+#endif /* !defined(_POWERMAC_DBDMA_H_) */
diff -r 015e6f9aed6e -r 4372af4d2175 sys/arch/macppc/dev/viareg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/macppc/dev/viareg.h Tue Jun 19 12:02:57 2001 +0000
@@ -0,0 +1,256 @@
+/* $NetBSD: viareg.h,v 1.4.8.2 2001/06/19 12:02:57 simonb Exp $ */
+
+/*-
+ * Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
+ * Michael L. Finch, Bradley A. Grantham, and
+ * Lawrence A. Kesteloot
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the Alice Group.
+ * 4. The names of the Alice Group or any of its members may not be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+
+ Prototype VIA control definitions
+
+ 06/04/92,22:33:57 BG Let's see what I can do.
+
+*/
+
+
+ /* VIA1 data register A */
+#define DA1I_vSCCWrReq 0x80
+#define DA1O_vPage2 0x40
+#define DA1I_CPU_ID1 0x40
+#define DA1O_vHeadSel 0x20
+#define DA1O_vOverlay 0x10
+#define DA1O_vSync 0x08
+#define DA1O_RESERVED2 0x04
+#define DA1O_RESERVED1 0x02
+#define DA1O_RESERVED0 0x01
+
+ /* VIA1 data register B */
+#define DB1I_Par_Err 0x80
+#define DB1O_vSndEnb 0x80
+#define DB1O_Par_Enb 0x40
+#define DB1O_vFDesk2 0x20
+#define DB1O_vFDesk1 0x10
+#define DB1I_vFDBInt 0x08
+#define DB1O_rTCEnb 0x04
+#define DB1O_rTCCLK 0x02
+#define DB1O_rTCData 0x01
+#define DB1I_rTCData 0x01
+
+ /* VIA2 data register A */
+#define DA2O_v2Ram1 0x80
+#define DA2O_v2Ram0 0x40
+#define DA2I_v2IRQ0 0x40
+#define DA2I_v2IRQE 0x20
+#define DA2I_v2IRQD 0x10
+#define DA2I_v2IRQC 0x08
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