Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/dev/sbus Purge C++-style comments.



details:   https://anonhg.NetBSD.org/src/rev/2db0ca8a36a1
branches:  trunk
changeset: 495197:2db0ca8a36a1
user:      mycroft <mycroft%NetBSD.org@localhost>
date:      Mon Jul 24 04:28:51 2000 +0000

description:
Purge C++-style comments.

diffstat:

 sys/dev/sbus/bereg.h |  146 ++++++++++++++++++++++++----------------------
 sys/dev/sbus/qereg.h |  160 ++++++++++++++++++++++++++------------------------
 2 files changed, 158 insertions(+), 148 deletions(-)

diffs (truncated from 365 to 300 lines):

diff -r 3b85d93cbf6a -r 2db0ca8a36a1 sys/dev/sbus/bereg.h
--- a/sys/dev/sbus/bereg.h      Mon Jul 24 04:13:45 2000 +0000
+++ b/sys/dev/sbus/bereg.h      Mon Jul 24 04:28:51 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bereg.h,v 1.3 1999/12/20 22:19:11 pk Exp $     */
+/*     $NetBSD: bereg.h,v 1.4 2000/07/24 04:28:51 mycroft Exp $        */
 
 /*-
  * Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -65,58 +65,60 @@
 
 /*
  * BE Global registers
- *-
+ */
+#if 0
 struct be_bregs {
-       u_int32_t xif_cfg;              // XIF config
-       u_int32_t _unused[63];          // reserved
-       u_int32_t stat;                 // status, clear on read
-       u_int32_t imask;                // interrupt mask
-       u_int32_t _unused2[64];         // reserved
-       u_int32_t tx_swreset;           // tx software reset
-       u_int32_t tx_cfg;               // tx config
-       u_int32_t ipkt_gap1;            // inter-packet gap 1
-       u_int32_t ipkt_gap2;            // inter-packet gap 2
-       u_int32_t attempt_limit;        // tx attempt limit
-       u_int32_t stime;                // tx slot time
-       u_int32_t preamble_len;         // size of tx preamble
-       u_int32_t preamble_pattern;     // pattern for tx preamble
-       u_int32_t tx_sframe_delim;      // tx delimiter
-       u_int32_t jsize;                // jam length
-       u_int32_t tx_pkt_max;           // tx max pkt size
-       u_int32_t tx_pkt_min;           // tx min pkt size
-       u_int32_t peak_attempt;         // count of tx peak attempts
-       u_int32_t dt_ctr;               // tx defer timer
-       u_int32_t nc_ctr;               // tx normal collision cntr
-       u_int32_t fc_ctr;               // tx first-collision cntr
-       u_int32_t ex_ctr;               // tx excess-collision cntr
-       u_int32_t lt_ctr;               // tx late-collision cntr
-       u_int32_t rand_seed;            // tx random number seed
-       u_int32_t tx_smachine;          // tx state machine
-       u_int32_t _unused3[44];         // reserved
-       u_int32_t rx_swreset;           // rx software reset
-       u_int32_t rx_cfg;               // rx config register
-       u_int32_t rx_pkt_max;           // rx max pkt size
-       u_int32_t rx_pkt_min;           // rx min pkt size
-       u_int32_t mac_addr2;            // ethernet address 2 (MSB)
-       u_int32_t mac_addr1;            // ethernet address 1
-       u_int32_t mac_addr0;            // ethernet address 0 (LSB)
-       u_int32_t fr_ctr;               // rx frame receive cntr
-       u_int32_t gle_ctr;              // rx giant-len error cntr
-       u_int32_t unale_ctr;            // rx unaligned error cntr
-       u_int32_t rcrce_ctr;            // rx CRC error cntr
-       u_int32_t rx_smachine;          // rx state machine
-       u_int32_t rx_cvalid;            // rx code violation
-       u_int32_t _unused4;             // reserved
-       u_int32_t htable3;              // hash table 3
-       u_int32_t htable2;              // hash table 2
-       u_int32_t htable1;              // hash table 1
-       u_int32_t htable0;              // hash table 0
-       u_int32_t afilter2;             // address filter 2
-       u_int32_t afilter1;             // address filter 1
-       u_int32_t afilter0;             // address filter 0
-       u_int32_t afilter_mask;         // address filter mask
+       u_int32_t xif_cfg;              /* XIF config */
+       u_int32_t _unused[63];          /* reserved */
+       u_int32_t stat;                 /* status, clear on read */
+       u_int32_t imask;                /* interrupt mask */
+       u_int32_t _unused2[64];         /* reserved */
+       u_int32_t tx_swreset;           /* tx software reset */
+       u_int32_t tx_cfg;               /* tx config */
+       u_int32_t ipkt_gap1;            /* inter-packet gap 1 */
+       u_int32_t ipkt_gap2;            /* inter-packet gap 2 */
+       u_int32_t attempt_limit;        /* tx attempt limit */
+       u_int32_t stime;                /* tx slot time */
+       u_int32_t preamble_len;         /* size of tx preamble */
+       u_int32_t preamble_pattern;     /* pattern for tx preamble */
+       u_int32_t tx_sframe_delim;      /* tx delimiter */
+       u_int32_t jsize;                /* jam length */
+       u_int32_t tx_pkt_max;           /* tx max pkt size */
+       u_int32_t tx_pkt_min;           /* tx min pkt size */
+       u_int32_t peak_attempt;         /* count of tx peak attempts */
+       u_int32_t dt_ctr;               /* tx defer timer */
+       u_int32_t nc_ctr;               /* tx normal collision cntr */
+       u_int32_t fc_ctr;               /* tx first-collision cntr */
+       u_int32_t ex_ctr;               /* tx excess-collision cntr */
+       u_int32_t lt_ctr;               /* tx late-collision cntr */
+       u_int32_t rand_seed;            /* tx random number seed */
+       u_int32_t tx_smachine;          /* tx state machine */
+       u_int32_t _unused3[44];         /* reserved */
+       u_int32_t rx_swreset;           /* rx software reset */
+       u_int32_t rx_cfg;               /* rx config register */
+       u_int32_t rx_pkt_max;           /* rx max pkt size */
+       u_int32_t rx_pkt_min;           /* rx min pkt size */
+       u_int32_t mac_addr2;            /* ethernet address 2 (MSB) */
+       u_int32_t mac_addr1;            /* ethernet address 1 */
+       u_int32_t mac_addr0;            /* ethernet address 0 (LSB) */
+       u_int32_t fr_ctr;               /* rx frame receive cntr */
+       u_int32_t gle_ctr;              /* rx giant-len error cntr */
+       u_int32_t unale_ctr;            /* rx unaligned error cntr */
+       u_int32_t rcrce_ctr;            /* rx CRC error cntr */
+       u_int32_t rx_smachine;          /* rx state machine */
+       u_int32_t rx_cvalid;            /* rx code violation */
+       u_int32_t _unused4;             /* reserved */
+       u_int32_t htable3;              /* hash table 3 */
+       u_int32_t htable2;              /* hash table 2 */
+       u_int32_t htable1;              /* hash table 1 */
+       u_int32_t htable0;              /* hash table 0 */
+       u_int32_t afilter2;             /* address filter 2 */
+       u_int32_t afilter1;             /* address filter 1 */
+       u_int32_t afilter0;             /* address filter 0 */
+       u_int32_t afilter_mask;         /* address filter mask */
 };
- * register indices: */
+#endif
+/* register indices: */
 #define BE_BRI_XIFCFG  (0*4)
 #define BE_BRI_STAT    (64*4)
 #define BE_BRI_IMASK   (65*4)
@@ -205,23 +207,25 @@
 
 /*
  * BE Channel registers
- *-
+ */
+#if 0
 struct be_cregs {
-       u_int32_t ctrl;         // control
-       u_int32_t stat;         // status
-       u_int32_t rxds;         // rx descriptor ring ptr
-       u_int32_t txds;         // tx descriptor ring ptr
-       u_int32_t rimask;       // rx interrupt mask
-       u_int32_t timask;       // tx interrupt mask
-       u_int32_t qmask;        // qec error interrupt mask
-       u_int32_t bmask;        // be error interrupt mask
-       u_int32_t rxwbufptr;    // local memory rx write ptr
-       u_int32_t rxrbufptr;    // local memory rx read ptr
-       u_int32_t txwbufptr;    // local memory tx write ptr
-       u_int32_t txrbufptr;    // local memory tx read ptr
-       u_int32_t ccnt;         // collision counter
+       u_int32_t ctrl;         /* control */
+       u_int32_t stat;         /* status */
+       u_int32_t rxds;         /* rx descriptor ring ptr */
+       u_int32_t txds;         /* tx descriptor ring ptr */
+       u_int32_t rimask;       /* rx interrupt mask */
+       u_int32_t timask;       /* tx interrupt mask */
+       u_int32_t qmask;        /* qec error interrupt mask */
+       u_int32_t bmask;        /* be error interrupt mask */
+       u_int32_t rxwbufptr;    /* local memory rx write ptr */
+       u_int32_t rxrbufptr;    /* local memory rx read ptr */
+       u_int32_t txwbufptr;    /* local memory tx write ptr */
+       u_int32_t txrbufptr;    /* local memory tx read ptr */
+       u_int32_t ccnt;         /* collision counter */
 };
- * register indices: */
+#endif
+/* register indices: */
 #define BE_CRI_CTRL    (0*4)
 #define BE_CRI_STAT    (1*4)
 #define BE_CRI_RXDS    (2*4)
@@ -266,12 +270,14 @@
 
 /*
  * BE Transceiver registers
- *-
+ */
+#if 0
 struct be_tregs {
-       u_int32_t       tcvr_pal;       // transceiver pal
-       u_int32_t       mgmt_pal;       // management pal
+       u_int32_t       tcvr_pal;       /* transceiver pal */
+       u_int32_t       mgmt_pal;       /* management pal */
 };
- * register indices: */
+#endif
+/* register indices: */
 #define BE_TRI_TCVRPAL 0
 #define BE_TRI_MGMTPAL 4
 
diff -r 3b85d93cbf6a -r 2db0ca8a36a1 sys/dev/sbus/qereg.h
--- a/sys/dev/sbus/qereg.h      Mon Jul 24 04:13:45 2000 +0000
+++ b/sys/dev/sbus/qereg.h      Mon Jul 24 04:28:51 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: qereg.h,v 1.2 1999/04/20 20:24:39 pk Exp $     */
+/*     $NetBSD: qereg.h,v 1.3 2000/07/24 04:28:51 mycroft Exp $        */
 
 /*-
  * Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -65,24 +65,26 @@
 
 /*
  * QE Channel registers
- *-
+ */
+#if 0
 struct qe_cregs {
-       u_int32_t ctrl;         // control
-       u_int32_t stat;         // status
-       u_int32_t rxds;         // rx descriptor ring ptr
-       u_int32_t txds;         // tx descriptor ring ptr
-       u_int32_t rimask;       // rx interrupt mask
-       u_int32_t timask;       // tx interrupt mask
-       u_int32_t qmask;        // qec error interrupt mask
-       u_int32_t mmask;        // mace error interrupt mask
-       u_int32_t rxwbufptr;    // local memory rx write ptr
-       u_int32_t rxrbufptr;    // local memory rx read ptr
-       u_int32_t txwbufptr;    // local memory tx write ptr
-       u_int32_t txrbufptr;    // local memory tx read ptr
-       u_int32_t ccnt;         // collision counter
-       u_int32_t pipg;         // inter-frame gap
+       u_int32_t ctrl;         /* control */
+       u_int32_t stat;         /* status */
+       u_int32_t rxds;         /* rx descriptor ring ptr */
+       u_int32_t txds;         /* tx descriptor ring ptr */
+       u_int32_t rimask;       /* rx interrupt mask */
+       u_int32_t timask;       /* tx interrupt mask */
+       u_int32_t qmask;        /* qec error interrupt mask */
+       u_int32_t mmask;        /* mace error interrupt mask */
+       u_int32_t rxwbufptr;    /* local memory rx write ptr */
+       u_int32_t rxrbufptr;    /* local memory rx read ptr */
+       u_int32_t txwbufptr;    /* local memory tx write ptr */
+       u_int32_t txrbufptr;    /* local memory tx read ptr */
+       u_int32_t ccnt;         /* collision counter */
+       u_int32_t pipg;         /* inter-frame gap */
 };
- * register indices: */
+#endif
+/* register indices: */
 #define QE_CRI_CTRL    (0*4)
 #define QE_CRI_STAT    (1*4)
 #define QE_CRI_RXDS    (2*4)
@@ -186,69 +188,71 @@
 
 /*
  * MACE registers
- *-
+ */
+#if 0
 struct qe_mregs {
-       u_int8_t rcvfifo;       [0]     // receive fifo
-       u_int8_t xmtfifo;       [1]     // transmit fifo
-       u_int8_t xmtfc;         [2]     // transmit frame control
-       u_int8_t xmtfs;         [3]     // transmit frame status
-       u_int8_t xmtrc;         [4]     // tx retry count
-       u_int8_t rcvfc;         [5]     // receive frame control
-       u_int8_t rcvfs;         [6]     // receive frame status
-       u_int8_t fifofc;        [7]     // fifo frame count
-       u_int8_t ir;            [8]     // interrupt register
-       u_int8_t imr;           [9]     // interrupt mask register
-       u_int8_t pr;            [10]    // poll register
-       u_int8_t biucc;         [11]    // biu config control
-       u_int8_t fifocc;        [12]    // fifo config control
-       u_int8_t maccc;         [13]    // mac config control
-       u_int8_t plscc;         [14]    // pls config control
-       u_int8_t phycc;         [15]    // phy config control
-       u_int8_t chipid1;       [16]    // chipid, low byte
-       u_int8_t chipid2;       [17]    // chipid, high byte
-       u_int8_t iac;           [18]    // internal address config
-       u_int8_t _reserved0;    [19]    // reserved
-       u_int8_t ladrf;         [20]    // logical address filter
-       u_int8_t padr;          [21]    // physical address
-       u_int8_t _reserved1;    [22]    // reserved
-       u_int8_t _reserved2;    [23]    // reserved
-       u_int8_t mpc;           [24]    // missed packet count
-       u_int8_t _reserved3;    [25]    // reserved
-       u_int8_t rntpc;         [26]    // runt packet count
-       u_int8_t rcvcc;         [27]    // receive collision count
-       u_int8_t _reserved4;    [28]    // reserved
-       u_int8_t utr;           [29]    // user test register
-       u_int8_t rtr1;          [30]    // reserved test register 1
-       u_int8_t rtr2;          [31]    // reserved test register 2
+       u_int8_t rcvfifo;       [0]     /* receive fifo */
+       u_int8_t xmtfifo;       [1]     /* transmit fifo */
+       u_int8_t xmtfc;         [2]     /* transmit frame control */
+       u_int8_t xmtfs;         [3]     /* transmit frame status */
+       u_int8_t xmtrc;         [4]     /* tx retry count */
+       u_int8_t rcvfc;         [5]     /* receive frame control */
+       u_int8_t rcvfs;         [6]     /* receive frame status */
+       u_int8_t fifofc;        [7]     /* fifo frame count */
+       u_int8_t ir;            [8]     /* interrupt register */
+       u_int8_t imr;           [9]     /* interrupt mask register */
+       u_int8_t pr;            [10]    /* poll register */
+       u_int8_t biucc;         [11]    /* biu config control */
+       u_int8_t fifocc;        [12]    /* fifo config control */
+       u_int8_t maccc;         [13]    /* mac config control */
+       u_int8_t plscc;         [14]    /* pls config control */
+       u_int8_t phycc;         [15]    /* phy config control */
+       u_int8_t chipid1;       [16]    /* chipid, low byte */
+       u_int8_t chipid2;       [17]    /* chipid, high byte */
+       u_int8_t iac;           [18]    /* internal address config */
+       u_int8_t _reserved0;    [19]    /* reserved */
+       u_int8_t ladrf;         [20]    /* logical address filter */
+       u_int8_t padr;          [21]    /* physical address */
+       u_int8_t _reserved1;    [22]    /* reserved */
+       u_int8_t _reserved2;    [23]    /* reserved */
+       u_int8_t mpc;           [24]    /* missed packet count */
+       u_int8_t _reserved3;    [25]    /* reserved */
+       u_int8_t rntpc;         [26]    /* runt packet count */
+       u_int8_t rcvcc;         [27]    /* receive collision count */



Home | Main Index | Thread Index | Old Index