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[src/trunk]: src/sys/arch/sparc64/include Add some alternate spellings for ASIs.
details: https://anonhg.NetBSD.org/src/rev/74a2e4130113
branches: trunk
changeset: 513674:74a2e4130113
user: eeh <eeh%NetBSD.org@localhost>
date: Mon Aug 06 23:55:34 2001 +0000
description:
Add some alternate spellings for ASIs.
Make sure ASI_PRIMARY_NOFAULT is always restored.
Garbage collect some old code.
diffstat:
sys/arch/sparc64/include/ctlreg.h | 598 ++++++-------------------------------
1 files changed, 95 insertions(+), 503 deletions(-)
diffs (truncated from 914 to 300 lines):
diff -r 40fa9896f8d6 -r 74a2e4130113 sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Mon Aug 06 23:28:53 2001 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Mon Aug 06 23:55:34 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.27 2001/07/19 23:47:37 eeh Exp $ */
+/* $NetBSD: ctlreg.h,v 1.28 2001/08/06 23:55:34 eeh Exp $ */
/*
* Copyright (c) 1996-2001 Eduardo Horvath
@@ -93,13 +93,13 @@
#define ASI_PRIMARY 0x80 /* [4u] primary address space */
#define ASI_SECONDARY 0x81 /* [4u] secondary address space */
-#define ASI_PRIMARY_NO_FAULT 0x82 /* [4u] primary address space, no fault */
-#define ASI_SECONDARY_NO_FAULT 0x83 /* [4u] secondary address space, no fault */
+#define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */
+#define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */
#define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */
#define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */
-#define ASI_PRIMARY_NO_FAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */
-#define ASI_SECONDARY_NO_FAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */
+#define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */
+#define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */
#define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */
#define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */
@@ -145,12 +145,12 @@
#define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE
#define ASI_P ASI_PRIMARY
#define ASI_S ASI_SECONDARY
-#define ASI_PNF ASI_PRIMARY_NO_FAULT
-#define ASI_SNF ASI_SECONDARY_NO_FAULT
+#define ASI_PNF ASI_PRIMARY_NOFAULT
+#define ASI_SNF ASI_SECONDARY_NOFAULT
#define ASI_PL ASI_PRIMARY_LITTLE
#define ASI_SL ASI_SECONDARY_LITTLE
-#define ASI_PNFL ASI_PRIMARY_NO_FAULT_LITTLE
-#define ASI_SNFL ASI_SECONDARY_NO_FAULT_LITTLE
+#define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE
+#define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE
#define ASI_FL8_P ASI_FL8_PRIMARY
#define ASI_FL8_S ASI_FL8_SECONDARY
#define ASI_FL16_P ASI_FL16_PRIMARY
@@ -172,6 +172,12 @@
#define ASI_BLK_S ASI_BLOCK_SECONDARY
#define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE
+/* Alternative spellings */
+#define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT
+#define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE
+#define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT
+#define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE
+
#define PHYS_ASI(x) (((x) | 0x08) == 0x1c)
#define LITTLE_ASI(x) ((x) & ASI_LITTLE)
@@ -476,12 +482,13 @@
__asm __volatile("wr %3,%%g0,%%asi; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
" lduba [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync" :
+" stxa %%g0,[%1] %4; membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lduba_v), "=r" (loc):
"r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
- __asm __volatile("wr %2,%%g0,%%asi; lduba [%1]%%asi,%0" :
+ __asm __volatile("wr %2,%%g0,%%asi; "
+" lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
"=r" (_lduba_v) :
"r" ((unsigned long)(loc)), "r" (asi));
}
@@ -499,13 +506,14 @@
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; rdpr %%pstate,%1; "
" sllx %3,32,%0; or %0,%2,%0; wrpr %1,8,%%pstate; "
" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" :
+" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; "
+" membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lduba_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) :
+" or %0,%1,%0; lduba [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduba_v) :
"r" ((unsigned long)(loc)),
"r" (_loc_hi), "r" (asi));
}
@@ -524,11 +532,13 @@
__asm __volatile("wr %3,%%g0,%%asi; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
" lduha [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lduha_v), "=r" (loc) :
+" stxa %%g0,[%1] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v), "=r" (loc) :
"r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
- __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0" :
+ __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; "
+" wr %%g0, 0x82, %%asi" :
"=r" (_lduha_v) :
"r" ((unsigned long)(loc)), "r" (asi));
}
@@ -546,13 +556,14 @@
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0; "
" or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" :
+" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; "
+" membar #Sync; wr %%g0, 0x82, %%asi" :
"=&r" (_lduha_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) :
+" or %0,%1,%0; lduha [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v) :
"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
}
return (_lduha_v);
@@ -571,7 +582,8 @@
__asm __volatile("wr %3,%%g0,%%asi; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
" lda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) :
+" stxa %%g0,[%1] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
"r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
@@ -592,11 +604,13 @@
__asm __volatile("wr %3,%%g0,%%asi; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
" ldswa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) :
+" stxa %%g0,[%1] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
"r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
- __asm __volatile("wr %2,%%g0,%%asi; ldswa [%1]%%asi,%0" :
+ __asm __volatile("wr %2,%%g0,%%asi; "
+" ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
"=r" (_lda_v) :
"r" ((unsigned long)(loc)), "r" (asi));
}
@@ -615,12 +629,13 @@
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; "
" sllx %3,32,%0; or %0,%2,%0; membar #Sync;lda [%0]%%asi,%0; "
" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %5; membar #Sync" : "=&r" (_lda_v), "=&r" (_pstate) :
+" stxa %%g0,[%1] %5; membar #Sync; "
+" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) :
+" or %0,%1,%0; lda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
"r" ((unsigned long)(loc)),
"r" (_loc_hi), "r" (asi));
}
@@ -638,13 +653,14 @@
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
" andn %2,0x1f,%0; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate; sllx %3,32,%0;"
" or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" :
+" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
+" wr %%g0, 0x82, %%asi" :
"=&r" (_lda_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) :
+" or %0,%1,%0; ldswa [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
"r" ((unsigned long)(loc)),
"r" (_loc_hi), "r" (asi));
}
@@ -663,11 +679,13 @@
__asm __volatile("wr %3,%%g0,%%asi; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
" ldda [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=&r" (loc) :
+" stxa %%g0,[%1] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (loc) :
"r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
- __asm __volatile("wr %2,%%g0,%%asi; ldda [%1]%%asi,%0" :
+ __asm __volatile("wr %2,%%g0,%%asi; "
+" ldda [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
"=r" (_lda_v) :
"r" ((unsigned long)(loc)), "r" (asi));
}
@@ -685,13 +703,14 @@
__asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; wrpr %1,8,%%pstate;"
" sllx %3,32,%0; or %0,%2,%0; membar #Sync; ldda [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync" :
+" andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
+" wr %%g0, 0x82, %%asi" :
"=&r" (_lda_v), "=&r" (_pstate) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) :
+" or %0,%1,%0; ldda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
"r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
}
return (_lda_v);
@@ -710,11 +729,13 @@
__asm __volatile("wr %3,%%g0,%%asi; "
" andn %2,0x1f,%0; stxa %%g0,[%0] %4; membar #Sync; "
" ldxa [%2]%%asi,%0; andn %2,0x1f,%1; membar #Sync; "
-" stxa %%g0,[%1] %4; membar #Sync" : "=&r" (_lda_v), "=r" (loc) :
+" stxa %%g0,[%1] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=r" (loc) :
"r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
- __asm __volatile("wr %2,%%g0,%%asi; ldxa [%1]%%asi,%0" :
+ __asm __volatile("wr %2,%%g0,%%asi; "
+" ldxa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
"=r" (_lda_v) :
"r" ((unsigned long)(loc)), "r" (asi));
}
@@ -733,13 +754,14 @@
" andn %2,0x1f,%0; rdpr %%pstate,%1; stxa %%g0,[%0] %5; "
" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; ldxa [%0]%%asi,%0; "
" wrpr %1,0,%%pstate; andn %2,0x1f,%1; membar #Sync; stxa %%g0,[%1] %5; membar #Sync; "
-" srlx %0,32,%1; srl %0,0,%0" :
+" srlx %0,32,%1; srl %0,0,%0; wr %%g0, 0x82, %%asi" :
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
-" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" :
+" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; "
+" srl %0,0,%0;; wr %%g0, 0x82, %%asi" :
"=&r" (_ldxa_lo), "=&r" (_ldxa_hi) :
"r" ((unsigned long)(loc)), "r" (_loc_hi),
"r" (asi));
@@ -755,12 +777,14 @@
{
if (PHYS_ASI(asi)) {
__asm __volatile("wr %3,%%g0,%%asi; stba %1,[%2]%%asi;"
-" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync" :
+" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" :
"=&r" (loc) :
"r" ((int)(value)), "r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG));
} else {
- __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi" : :
+ __asm __volatile("wr %2,%%g0,%%asi; stba %0,[%1]%%asi; "
+" wr %%g0, 0x82, %%asi" : :
"r" ((int)(value)), "r" ((unsigned long)(loc)),
"r" (asi));
}
@@ -775,13 +799,14 @@
if (PHYS_ASI(asi)) {
__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;"
" or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate; "
-" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync" :
+" andn %0,0x1f,%1; membar #Sync; stxa %%g0,[%1] %6; membar #Sync; "
+" wr %%g0, 0x82, %%asi" :
"=&r" (_loc_hi), "=&r" (_pstate) :
"r" ((int)(value)), "r" ((unsigned long)(loc)),
"r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG));
} else {
__asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
-" or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) :
+" or %2,%0,%0; stba %1,[%0]%%asi; wr %%g0, 0x82, %%asi" : "=&r" (_loc_hi) :
"r" ((int)(value)), "r" ((unsigned long)(loc)),
"r" (_loc_hi), "r" (asi));
}
@@ -795,12 +820,14 @@
{
if (PHYS_ASI(asi)) {
__asm __volatile("wr %3,%%g0,%%asi; stha %1,[%2]%%asi;"
-" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync" :
+" andn %2,0x1f,%0; membar #Sync; stxa %%g0,[%0] %4; membar #Sync; "
+" wr %%g0, 0x82, %%asi" :
"=&r" (loc) :
"r" ((int)(value)), "r" ((unsigned long)(loc)),
"r" (asi), "n" (ASI_DCACHE_TAG) : "memory");
} else {
- __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi" : :
+ __asm __volatile("wr %2,%%g0,%%asi; stha %0,[%1]%%asi; "
+" wr %%g0, 0x82, %%asi" : :
"r" ((int)(value)), "r" ((unsigned long)(loc)),
"r" (asi) : "memory");
}
@@ -815,14 +842,15 @@
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