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[src/trunk]: src/sys/arch Switch kernels for Lubbock and TwinTail to use pmap...
details: https://anonhg.NetBSD.org/src/rev/f237e3915393
branches: trunk
changeset: 579556:f237e3915393
user: bsh <bsh%NetBSD.org@localhost>
date: Thu Mar 17 16:22:56 2005 +0000
description:
Switch kernels for Lubbock and TwinTail to use pmap_devmap to map
I/O registers that are used in early start-up stage. Also stop using
special bootstrap-time-only bus_space_map function in {lubbock,g42xxeb}_machdep.c.
This makes initarm() for them a bit simpler, and gives us smaller diffs
to other evbarm platforms.
diffstat:
sys/arch/arm/xscale/pxa2x0_space.c | 26 ++-
sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c | 199 ++++++++++-------------------
sys/arch/evbarm/g42xxeb/g42xxeb_reg.h | 8 +-
sys/arch/evbarm/lubbock/lubbock_machdep.c | 193 +++++++++-------------------
sys/arch/evbarm/lubbock/lubbock_reg.h | 7 +-
5 files changed, 155 insertions(+), 278 deletions(-)
diffs (truncated from 724 to 300 lines):
diff -r ca8d3256451c -r f237e3915393 sys/arch/arm/xscale/pxa2x0_space.c
--- a/sys/arch/arm/xscale/pxa2x0_space.c Thu Mar 17 15:51:28 2005 +0000
+++ b/sys/arch/arm/xscale/pxa2x0_space.c Thu Mar 17 16:22:56 2005 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pxa2x0_space.c,v 1.5 2004/06/07 19:45:22 nathanw Exp $ */
+/* $NetBSD: pxa2x0_space.c,v 1.6 2005/03/17 16:22:56 bsh Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pxa2x0_space.c,v 1.5 2004/06/07 19:45:22 nathanw Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pxa2x0_space.c,v 1.6 2005/03/17 16:22:56 bsh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -175,13 +175,12 @@
u_long startpa, endpa, pa;
vaddr_t va;
pt_entry_t *pte;
+ const struct pmap_devmap *pd;
- if ((u_long)bpa > (u_long)KERNEL_BASE) {
- /* Some IO registers (ex. UART ports for console)
- are mapped to fixed address by board specific
- routine. */
- *bshp = bpa;
- return(0);
+ if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
+ /* Device was statically mapped. */
+ *bshp = pd->pd_va + (bpa - pd->pd_pa);
+ return 0;
}
startpa = trunc_page(bpa);
@@ -214,11 +213,18 @@
void
pxa2x0_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
{
+ vaddr_t va;
+ vaddr_t endva;
- if (bsh > (u_long)KERNEL_BASE)
+ if (pmap_devmap_find_va(bsh, size) != NULL) {
+ /* Device was statically mapped; nothing to do. */
return;
+ }
- uvm_km_free(kernel_map, bsh, size);
+ endva = round_page(bsh + size);
+ va = trunc_page(bsh);
+
+ uvm_km_free(kernel_map, va, endva - va);
}
diff -r ca8d3256451c -r f237e3915393 sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c
--- a/sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c Thu Mar 17 15:51:28 2005 +0000
+++ b/sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c Thu Mar 17 16:22:56 2005 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: g42xxeb_machdep.c,v 1.1 2005/02/26 10:49:53 bsh Exp $ */
+/* $NetBSD: g42xxeb_machdep.c,v 1.2 2005/03/17 16:22:57 bsh Exp $ */
/*
* Copyright (c) 2002, 2003, 2004, 2005 Genetec Corporation.
@@ -342,111 +342,65 @@
}
/*
- * Mapping table for core kernel memory. These areas are mapped in
- * init time at fixed virtual address with section mappings.
+ * Static device mappings. These peripheral registers are mapped at
+ * fixed virtual addresses very early in initarm() so that we can use
+ * them while booting the kernel, and stay at the same address
+ * throughout whole kernel's life time.
+ *
+ * We use this table twice; once with bootstrap page table, and once
+ * with kernel's page table which we build up in initarm().
+ *
+ * Since we map these registers into the bootstrap page table using
+ * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map
+ * registers segment-aligned and segment-rounded in order to avoid
+ * using the 2nd page tables.
*/
-struct l1_sec_map {
- vaddr_t va;
- vaddr_t pa;
- vsize_t size;
- int flags;
-} l1_sec_table[] = {
+
+#define _A(a) ((a) & ~L1_S_OFFSET)
+#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
+
+static const struct pmap_devmap g42xxeb_devmap[] = {
{
G42XXEB_PLDREG_VBASE,
- G42XXEB_PLDREG_BASE,
- G42XXEB_PLDREG_SIZE,
- PTE_NOCACHE,
+ _A(G42XXEB_PLDREG_BASE),
+ _S(G42XXEB_PLDREG_SIZE),
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE,
},
{
G42XXEB_GPIO_VBASE,
- PXA2X0_GPIO_BASE,
- PXA2X0_GPIO_SIZE,
- PTE_NOCACHE,
+ _A(PXA2X0_GPIO_BASE),
+ _S(PXA2X0_GPIO_SIZE),
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE,
},
{
G42XXEB_CLKMAN_VBASE,
- PXA2X0_CLKMAN_BASE,
- PXA2X0_CLKMAN_SIZE,
- PTE_NOCACHE,
+ _A(PXA2X0_CLKMAN_BASE),
+ _S(PXA2X0_CLKMAN_SIZE),
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE,
},
{
G42XXEB_INTCTL_VBASE,
- PXA2X0_INTCTL_BASE,
- PXA2X0_INTCTL_SIZE,
- PTE_NOCACHE,
+ _A(PXA2X0_INTCTL_BASE),
+ _S(PXA2X0_INTCTL_SIZE),
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE,
+ },
+ {
+ G42XXEB_FFUART_VBASE,
+ _A(PXA2X0_FFUART_BASE),
+ _S(4 * COM_NPORTS),
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE,
+ },
+ {
+ G42XXEB_BTUART_VBASE,
+ _A(PXA2X0_BTUART_BASE),
+ _S(4 * COM_NPORTS),
+ VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE,
},
{0, 0, 0, 0,}
};
-static void
-map_io_area(paddr_t pagedir)
-{
- int loop;
-
- /*
- * Map devices we can map w/ section mappings.
- */
- loop = 0;
- while (l1_sec_table[loop].size) {
- vm_size_t sz;
-
-#ifdef VERBOSE_INIT_ARM
- printf("%08lx -> %08lx @ %08lx\n", l1_sec_table[loop].pa,
- l1_sec_table[loop].pa + l1_sec_table[loop].size - 1,
- l1_sec_table[loop].va);
-#endif
- for (sz = 0; sz < l1_sec_table[loop].size; sz += L1_S_SIZE)
- pmap_map_section(pagedir, l1_sec_table[loop].va + sz,
- l1_sec_table[loop].pa + sz,
- VM_PROT_READ|VM_PROT_WRITE,
- l1_sec_table[loop].flags);
- ++loop;
- }
-}
-
-/*
- * simple memory mapping function used in early bootstrap stage
- * before pmap is initialized.
- * size and cacheability are ignored and map one section with nocache.
- */
-static vaddr_t section_free = G42XXEB_VBASE_FREE;
-
-static int
-bootstrap_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
- int cacheable, bus_space_handle_t *bshp)
-{
- u_long startpa;
- vaddr_t va;
- pd_entry_t *pagedir = read_ttb();
- /* This assumes PA==VA for page directory */
-
- va = section_free;
- section_free += L1_S_SIZE;
-
- startpa = trunc_page(bpa);
- pmap_map_section((vaddr_t)pagedir, va, startpa,
- VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
- cpu_tlb_flushD();
-
- *bshp = (bus_space_handle_t)(va + (bpa - startpa));
-
- return(0);
-}
-
-static void
-copy_io_area_map(pd_entry_t *new_pd)
-{
- pd_entry_t *cur_pd = read_ttb();
- vaddr_t va;
-
- for (va = G42XXEB_IO_AREA_VBASE;
- (cur_pd[va>>L1_S_SHIFT] & L1_TYPE_MASK) == L1_TYPE_S;
- va += L1_S_SIZE) {
-
- new_pd[va>>L1_S_SHIFT] = cur_pd[va>>L1_S_SHIFT];
- }
-}
-
+#undef _A
+#undef _S
/*
@@ -476,8 +430,6 @@
#ifdef DIAGNOSTIC
extern vsize_t xscale_minidata_clean_size; /* used in KASSERT */
#endif
- int (*map_func_save)(void *, bus_addr_t, bus_size_t, int,
- bus_space_handle_t *);
#define LEDSTEP_P() ioreg8_write(G42XXEB_PLDREG_BASE+G42XXEB_LED, led_data++)
#define LEDSTEP() pldreg8_write(G42XXEB_LED, led_data++);
@@ -485,22 +437,25 @@
/* use physical address until pagetable is set */
LEDSTEP_P();
+ /* map some peripheral registers at static I/O area */
+ pmap_devmap_bootstrap((vaddr_t)read_ttb(), g42xxeb_devmap);
+
+ LEDSTEP_P();
+
/* start 32.768KHz OSC */
- ioreg_write(PXA2X0_CLKMAN_BASE + 0x08, 2);
+ ioreg_write(G42XXEB_CLKMAN_VBASE + 0x08, 2);
+ /* Get ready for splfoo() */
+ pxa2x0_intr_bootstrap(G42XXEB_INTCTL_VBASE);
+
+ LEDSTEP();
/*
* Heads up ... Setup the CPU / MMU / TLB functions
*/
if (set_cpufuncs())
panic("cpu not recognized!");
- LEDSTEP_P();
- /* Get ready for splfoo() */
- pxa2x0_intr_bootstrap(PXA2X0_INTCTL_BASE);
-
-#if 0
- /* Calibrate the delay loop. */
-#endif
+ LEDSTEP();
/*
* Okay, RedBoot has provided us with the following memory map:
@@ -528,7 +483,9 @@
* 0xc0000000 - 0xcfffffff Y Y Y Cache Flush Region
* (done by this routine)
* 0xfd000000 - 0xfd0000ff N N N I/O baseboard registers
- * 0xfd100000 - 0xfd2fffff N N N Processor Registers.
+ * 0xfd100000 - 0xfd3fffff N N N Processor Registers.
+ * 0xfd400000 - 0xfd4fffff N N N FF-UART
+ * 0xfd500000 - 0xfd5fffff N N N BT-UART
*
* The first level page table is at 0xa0004000. There are also
* 2 second-level tables at 0xa0008000 and 0xa0008400.
@@ -537,22 +494,6 @@
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
- /*
- * map PLD registers to fixed address.
- */
- {
- /*
- * Tweak RedBoot's pagetable so that we can access to
- * some registers at same VA before and after installing
- * our page table.
- */
- paddr_t ttb = (paddr_t)read_ttb();
-
- map_io_area(ttb);
- cpu_tlb_flushD();
- }
-
- /* now we can access LED at new virtual address */
LEDSTEP();
/* setup GPIO for BTUART, in case bootloader doesn't take care of it */
@@ -564,12 +505,6 @@
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