[src/trunk]: src/sys/arch/mips Add a hint variable (mips_sdcache_forceinv, ex...

[sekiya <sekiya%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/63184ac2c53d
branches:  trunk
changeset: 574477:63184ac2c53d
user:      sekiya <sekiya%NetBSD.org@localhost>
date:      Tue Mar 01 04:23:44 2005 +0000

description:
Add a hint variable (mips_sdcache_forceinv, explicitly initialized to zero)
that tells pmap_zero_page() and pmap_copy_page() to unconditionally invalidate
pages for r5k-class CPUs with secondary cache.

This behavior must be explicitly enabled by setting mips_sdcache_forceinv to 1.

This is the last bit of a patch that has been kicked around since 2000 between
rafal@, tsutsui@, and myself.

diffstat:

 sys/arch/mips/include/cache.h |   4 +++-
 sys/arch/mips/mips/cache.c    |   6 ++++--
 sys/arch/mips/mips/pmap.c     |  13 ++++++++-----
 3 files changed, 15 insertions(+), 8 deletions(-)

diffs (93 lines):

diff -r 82754cd91b0e -r 63184ac2c53d sys/arch/mips/include/cache.h
--- a/sys/arch/mips/include/cache.h     Tue Mar 01 03:31:45 2005 +0000
+++ b/sys/arch/mips/include/cache.h     Tue Mar 01 04:23:44 2005 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
+/*     $NetBSD: cache.h,v 1.7 2005/03/01 04:23:44 sekiya Exp $ */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -185,6 +185,8 @@
 
 extern int mips_scache_unified;
 
+extern u_int mips_sdcache_forceinv;    /* force pmap to invalidate for r5ksc */
+
 /* TERTIARY CACHE VARIABLES */
 extern u_int mips_tcache_size;         /* always unified */
 extern u_int mips_tcache_line_size;
diff -r 82754cd91b0e -r 63184ac2c53d sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Tue Mar 01 03:31:45 2005 +0000
+++ b/sys/arch/mips/mips/cache.c        Tue Mar 01 04:23:44 2005 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.25 2004/12/13 08:39:21 sekiya Exp $        */
+/*     $NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $        */
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.25 2004/12/13 08:39:21 sekiya Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.26 2005/03/01 04:23:44 sekiya Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -129,6 +129,8 @@
 
 int mips_scache_unified;
 
+u_int mips_sdcache_forceinv = 0;
+
 /* TERTIARY CACHE VARIABLES */
 u_int mips_tcache_size;                /* always unified */
 u_int mips_tcache_line_size;
diff -r 82754cd91b0e -r 63184ac2c53d sys/arch/mips/mips/pmap.c
--- a/sys/arch/mips/mips/pmap.c Tue Mar 01 03:31:45 2005 +0000
+++ b/sys/arch/mips/mips/pmap.c Tue Mar 01 04:23:44 2005 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.156 2005/01/17 04:54:14 atatat Exp $        */
+/*     $NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $        */
 
 /*-
  * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@@ -74,7 +74,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.156 2005/01/17 04:54:14 atatat Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.157 2005/03/01 04:23:44 sekiya Exp $");
 
 /*
  *     Manages physical address maps.
@@ -1598,7 +1598,8 @@
         *
         * XXXJRT This is totally disgusting.
         */
-       if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
+       if (MIPS_HAS_R4K_MMU &&
+               ( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv) ) )
                mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
 #endif /* MIPS3_PLUS */
 }
@@ -1635,7 +1636,8 @@
         * It would probably be better to map the destination as a
         * write-through no allocate to reduce cache thrash.
         */
-       if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
+       if (MIPS_HAS_R4K_MMU &&
+               ( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
                /*XXX FIXME Not very sophisticated */
                mips_flushcache_allpvh(src);
 /*             mips_flushcache_allpvh(dst); */
@@ -1657,7 +1659,8 @@
         *
         * XXXJRT -- This is totally disgusting.
         */
-       if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
+       if (MIPS_HAS_R4K_MMU &&
+               ( (mips_sdcache_line_size == 0) || (mips_sdcache_forceinv)) ) {
                mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
                mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
        }