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[src/trunk]: src/sys/arch convert PRID handling to use macros on an int, not ...
details: https://anonhg.NetBSD.org/src/rev/47599750ac1d
branches: trunk
changeset: 495416:47599750ac1d
user: cgd <cgd%NetBSD.org@localhost>
date: Thu Jul 27 17:29:05 2000 +0000
description:
convert PRID handling to use macros on an int, not bit-fields.
there's no reason to use bit-fields, and they just complexity to
the header.
diffstat:
sys/arch/hpcmips/tx/tx39.c | 7 +++----
sys/arch/mips/include/locore.h | 30 +++++++++++-------------------
sys/arch/mips/mips/mips_machdep.c | 39 +++++++++++++++++++++++----------------
3 files changed, 37 insertions(+), 39 deletions(-)
diffs (182 lines):
diff -r 0d514cef0da7 -r 47599750ac1d sys/arch/hpcmips/tx/tx39.c
--- a/sys/arch/hpcmips/tx/tx39.c Thu Jul 27 17:18:19 2000 +0000
+++ b/sys/arch/hpcmips/tx/tx39.c Thu Jul 27 17:29:05 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tx39.c,v 1.18 2000/05/22 17:17:44 uch Exp $ */
+/* $NetBSD: tx39.c,v 1.19 2000/07/27 17:29:05 cgd Exp $ */
/*-
* Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved.
@@ -117,13 +117,12 @@
platform.reboot = tx_reboot;
platform.iointr = tx39icu_intr;
- model = (cpu_id.cpu.cp_majrev << 4)| cpu_id.cpu.cp_minrev;
+ model = MIPS_PRID_REV(cpu_id);
switch (model) {
default:
/* Unknown TOSHIBA TX39-series */
- sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x.%x",
- cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev);
+ sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x", model);
break;
case TMPR3912:
tx39clock_cpuspeed(&cpuclock, &cpuspeed);
diff -r 0d514cef0da7 -r 47599750ac1d sys/arch/mips/include/locore.h
--- a/sys/arch/mips/include/locore.h Thu Jul 27 17:18:19 2000 +0000
+++ b/sys/arch/mips/include/locore.h Thu Jul 27 17:29:05 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.39 2000/07/20 18:33:40 jeffs Exp $ */
+/* $NetBSD: locore.h,v 1.40 2000/07/27 17:29:06 cgd Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -188,23 +188,14 @@
/*
* CPU identification, from PRID register.
*/
-union cpuprid {
- int cpuprid;
- struct {
-#if BYTE_ORDER == BIG_ENDIAN
- u_int pad1:16; /* reserved */
- u_int cp_imp:8; /* implementation identifier */
- u_int cp_majrev:4; /* major revision identifier */
- u_int cp_minrev:4; /* minor revision identifier */
-#else
- u_int cp_minrev:4; /* minor revision identifier */
- u_int cp_majrev:4; /* major revision identifier */
- u_int cp_imp:8; /* implementation identifier */
- u_int pad1:16; /* reserved */
-#endif
- } cpu;
-};
+typedef int mips_prid_t;
+#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
+#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
+#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
+
+#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
+#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
#ifdef _KERNEL
@@ -212,8 +203,9 @@
* Global variables used to communicate CPU type, and parameters
* such as cache size, from locore to higher-level code (e.g., pmap).
*/
-extern union cpuprid cpu_id;
-extern union cpuprid fpu_id;
+
+extern mips_prid_t cpu_id;
+extern mips_prid_t fpu_id;
extern int cpu_arch;
extern int mips_num_tlb_entries;
extern u_int mips_L1DCacheSize;
diff -r 0d514cef0da7 -r 47599750ac1d sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Thu Jul 27 17:18:19 2000 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Thu Jul 27 17:29:05 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.97 2000/07/27 08:28:36 jeffs Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.98 2000/07/27 17:29:06 cgd Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.97 2000/07/27 08:28:36 jeffs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.98 2000/07/27 17:29:06 cgd Exp $");
#include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h"
@@ -341,7 +341,7 @@
* Clear out the I and D caches.
*/
- switch (cpu_id.cpu.cp_imp) {
+ switch (MIPS_PRID_IMPL(cpu_id)) {
#ifdef MIPS1
case MIPS_R2000:
case MIPS_R3000:
@@ -351,7 +351,7 @@
#ifdef ENABLE_MIPS_TX3900
case MIPS_TX3900:
cpu_arch = 1;
- switch (cpu_id.cpu.cp_majrev) {
+ switch (MIPS_PRID_REV_MAJ(cpu_id)) {
default:
panic("not supported revision");
case 1: /* TX3912 */
@@ -418,7 +418,7 @@
#endif /* MIPS3 */
default:
- printf("CPU type (0x%x) not supported\n", cpu_id.cpuprid);
+ printf("CPU type (0x%x) not supported\n", cpu_id);
cpu_reboot(RB_HALT, NULL);
}
@@ -523,41 +523,48 @@
cpuname = NULL;
for (i = 0; i < sizeof(cputab)/sizeof(cputab[0]); i++) {
- if (cpu_id.cpu.cp_imp == cputab[i].cpu_imp) {
+ if (MIPS_PRID_IMPL(cpu_id) == cputab[i].cpu_imp) {
cpuname = cputab[i].cpu_name;
break;
}
}
- if (cpu_id.cpu.cp_imp == MIPS_R4000 && mips_L1ICacheSize == 16384)
+ if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4000 && mips_L1ICacheSize == 16384)
cpuname = "MIPS R4400 CPU";
fpuname = NULL;
for (i = 0; i < sizeof(fputab)/sizeof(fputab[0]); i++) {
- if (fpu_id.cpu.cp_imp == fputab[i].cpu_imp) {
+ if (MIPS_PRID_IMPL(fpu_id) == fputab[i].cpu_imp) {
fpuname = fputab[i].cpu_name;
break;
}
}
- if (fpuname == NULL && fpu_id.cpu.cp_imp == cpu_id.cpu.cp_imp)
+ if (fpuname == NULL && MIPS_PRID_IMPL(fpu_id) == MIPS_PRID_IMPL(cpu_id))
fpuname = "built-in FPU";
- if (cpu_id.cpu.cp_imp == MIPS_R4700) /* FPU PRid is 0x20 */
+ if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4700) /* FPU PRid is 0x20 */
fpuname = "built-in FPU";
- if (cpu_id.cpu.cp_imp == MIPS_RC64470) /* FPU PRid is 0x21 */
+ if (MIPS_PRID_IMPL(cpu_id) == MIPS_RC64470) /* FPU PRid is 0x21 */
fpuname = "built-in FPU";
if (cpuname != NULL)
- printf("%s (0x%x)", cpuname, cpu_id.cpuprid);
+ printf("%s (0x%x)", cpuname, cpu_id);
else
- printf("unknown CPU type (0x%x)", cpu_id.cpuprid);
- printf(" Rev. %d.%d", cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev);
+ printf("unknown CPU type (0x%x)", cpu_id);
+ printf(" Rev. %d.%d", MIPS_PRID_REV_MAJ(cpu_id),
+ MIPS_PRID_REV_MIN(cpu_id));
if (fpuname != NULL)
printf(" with %s", fpuname);
else
- printf(" with unknown FPC type (0x%x)", fpu_id.cpu.cp_imp);
- printf(" Rev. %d.%d", fpu_id.cpu.cp_majrev, fpu_id.cpu.cp_minrev);
+ printf(" with unknown FPC type (0x%x)", fpu_id);
+ printf(" Rev. %d.%d", MIPS_PRID_REV_MAJ(fpu_id),
+ MIPS_PRID_REV_MIN(fpu_id));
printf("\n");
+ if (MIPS_PRID_RSVD(cpu_id) != 0) {
+ printf("cpu0: NOTE: top 16 bits of PRID not 0!\n");
+ printf("cpu0: Please mail port-mips%netbsd.org@localhost with cpu0 dmesg lines.\n");
+ }
+
printf("cpu0: ");
#ifdef MIPS1
if (cpu_arch == 1) {
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