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[src/trunk]: src/sys/arch/sparc64/dev Sun Blade 100 support (and some psycho ...
details: https://anonhg.NetBSD.org/src/rev/5cd6ee675231
branches: trunk
changeset: 514790:5cd6ee675231
user: eeh <eeh%NetBSD.org@localhost>
date: Mon Sep 10 16:17:06 2001 +0000
description:
Sun Blade 100 support (and some psycho fixes from Jason Wright).
diffstat:
sys/arch/sparc64/dev/ebus.c | 10 ++++++-
sys/arch/sparc64/dev/psycho.c | 60 ++++++++++++++++++++++++++++-----------
sys/arch/sparc64/dev/psychoreg.h | 33 +++++++++++----------
3 files changed, 69 insertions(+), 34 deletions(-)
diffs (255 lines):
diff -r c2865d4c60fb -r 5cd6ee675231 sys/arch/sparc64/dev/ebus.c
--- a/sys/arch/sparc64/dev/ebus.c Mon Sep 10 15:47:38 2001 +0000
+++ b/sys/arch/sparc64/dev/ebus.c Mon Sep 10 16:17:06 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ebus.c,v 1.24 2001/07/25 03:49:54 eeh Exp $ */
+/* $NetBSD: ebus.c,v 1.25 2001/09/10 16:17:06 eeh Exp $ */
/*
* Copyright (c) 1999, 2000 Matthew R. Green
@@ -140,6 +140,14 @@
strcmp(name, "ebus") == 0)
return (1);
+ /* Or a real ebus III */
+ OF_getprop(node, "name", &name, sizeof(name));
+ if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
+ PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN &&
+ PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_EBUSIII &&
+ strcmp(name, "ebus") == 0)
+ return (1);
+
/* Or a PCI-ISA bridge XXX I hope this is on-board. */
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA) {
diff -r c2865d4c60fb -r 5cd6ee675231 sys/arch/sparc64/dev/psycho.c
--- a/sys/arch/sparc64/dev/psycho.c Mon Sep 10 15:47:38 2001 +0000
+++ b/sys/arch/sparc64/dev/psycho.c Mon Sep 10 16:17:06 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: psycho.c,v 1.34 2001/07/20 00:07:13 eeh Exp $ */
+/* $NetBSD: psycho.c,v 1.35 2001/09/10 16:17:06 eeh Exp $ */
/*
* Copyright (c) 1999, 2000 Matthew R. Green
@@ -169,10 +169,20 @@
* We really should attach handlers for each.
*
*/
+
#define ROM_PCI_NAME "pci"
-#define ROM_SABRE_MODEL "SUNW,sabre"
-#define ROM_SIMBA_MODEL "SUNW,simba"
-#define ROM_PSYCHO_MODEL "SUNW,psycho"
+
+struct psycho_names {
+ char *p_name;
+ int p_type;
+} psycho_names[] = {
+ { "SUNW,psycho", PSYCHO_MODE_PSYCHO },
+ { "pci108e,8000", PSYCHO_MODE_PSYCHO },
+ { "SUNW,sabre", PSYCHO_MODE_SABRE },
+ { "pci108e,a000", PSYCHO_MODE_SABRE },
+ { "pci108e,a001", PSYCHO_MODE_SABRE },
+ { NULL, 0 }
+};
static int
psycho_match(parent, match, aux)
@@ -182,13 +192,19 @@
{
struct mainbus_attach_args *ma = aux;
char *model = getpropstring(ma->ma_node, "model");
+ int i;
/* match on a name of "pci" and a sabre or a psycho */
- if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0 &&
- (strcmp(model, ROM_SABRE_MODEL) == 0 ||
- strcmp(model, ROM_PSYCHO_MODEL) == 0))
- return (1);
+ if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) {
+ for (i=0; psycho_names[i].p_name; i++)
+ if (strcmp(model, psycho_names[i].p_name) == 0)
+ return (1);
+ model = getpropstring(ma->ma_node, "compatible");
+ for (i=0; psycho_names[i].p_name; i++)
+ if (strcmp(model, psycho_names[i].p_name) == 0)
+ return (1);
+ }
return (0);
}
@@ -216,7 +232,7 @@
struct mainbus_attach_args *ma = aux;
bus_space_handle_t bh;
u_int64_t csr;
- int psycho_br[2], n;
+ int psycho_br[2], n, i;
struct pci_ctl *pci_ctl;
char *model = getpropstring(ma->ma_node, "model");
@@ -229,13 +245,21 @@
/*
* call the model-specific initialisation routine.
*/
+ for (i=0; psycho_names[i].p_name; i++)
+ if (strcmp(model, psycho_names[i].p_name) == 0) {
+ sc->sc_mode = psycho_names[i].p_type;
+ goto found;
+ }
- if (strcmp(model, ROM_SABRE_MODEL) == 0)
- sc->sc_mode = PSYCHO_MODE_SABRE;
- else if (strcmp(model, ROM_PSYCHO_MODEL) == 0)
- sc->sc_mode = PSYCHO_MODE_PSYCHO;
- else
- panic("psycho_attach: unknown model %s?", model);
+ model = getpropstring(ma->ma_node, "compatible");
+ for (i=0; psycho_names[i].p_name; i++)
+ if (strcmp(model, psycho_names[i].p_name) == 0) {
+ sc->sc_mode = psycho_names[i].p_type;
+ goto found;
+ }
+
+ panic("unknown psycho model %s", model);
+found:
/*
* The psycho gets three register banks:
@@ -600,7 +624,8 @@
panic("%s: PCI bus A error AFAR %llx AFSR %llx\n",
sc->sc_dev.dv_xname,
- (long long)regs->psy_ue_afar, (long long)regs->psy_ue_afsr);
+ (long long)regs->psy_pcictl[0].pci_afar,
+ (long long)regs->psy_pcictl[0].pci_afsr);
return (1);
}
static int
@@ -616,7 +641,8 @@
panic("%s: PCI bus B error AFAR %llx AFSR %llx\n",
sc->sc_dev.dv_xname,
- (long long)regs->psy_ue_afar, (long long)regs->psy_ue_afsr);
+ (long long)regs->psy_pcictl[0].pci_afar,
+ (long long)regs->psy_pcictl[0].pci_afsr);
return (1);
}
static int
diff -r c2865d4c60fb -r 5cd6ee675231 sys/arch/sparc64/dev/psychoreg.h
--- a/sys/arch/sparc64/dev/psychoreg.h Mon Sep 10 15:47:38 2001 +0000
+++ b/sys/arch/sparc64/dev/psychoreg.h Mon Sep 10 16:17:06 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: psychoreg.h,v 1.7 2001/07/20 00:07:13 eeh Exp $ */
+/* $NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp $ */
/*
* Copyright (c) 1998, 1999 Eduardo E. Horvath
@@ -95,7 +95,7 @@
u_int64_t pcib_slot2_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c30 */
u_int64_t pcib_slot3_int; /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c38 */
- u_int64_t pad5[120];
+ u_int64_t pad4[120];
u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.1000 */
u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.1008 */
@@ -119,7 +119,7 @@
u_int64_t ffb0_int_map; /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */
u_int64_t ffb1_int_map; /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */
- u_int64_t pad6[107];
+ u_int64_t pad5[107];
/* Note: clear interrupt 0 registers are not really used */
u_int64_t pcia0_clr_int[4]; /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */
@@ -131,7 +131,7 @@
u_int64_t pcib2_clr_int[4]; /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */
u_int64_t pcib3_clr_int[4]; /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */
- u_int64_t pad8[96];
+ u_int64_t pad6[96];
u_int64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.1800 */
u_int64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.1808 */
@@ -153,11 +153,11 @@
u_int64_t pciberr_clr_int; /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */
u_int64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */
- u_int64_t pad9[45];
+ u_int64_t pad7[45];
u_int64_t intr_retry_timer; /* interrupt retry timer */ /* 1fe.0000.1a00 */
- u_int64_t pad10[63];
+ u_int64_t pad8[63];
struct timer_counter {
u_int64_t tc_count; /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */
@@ -166,55 +166,56 @@
u_int64_t pci_dma_write_sync; /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */
- u_int64_t pad11[123];
+ u_int64_t pad9[123];
struct pci_ctl {
u_int64_t pci_csr; /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */
+ u_int64_t pad10;
u_int64_t pci_afsr; /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */
u_int64_t pci_afar; /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */
u_int64_t pci_diag; /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */
u_int64_t pci_tasr; /* PCI target address space reg (IIi)*/ /* 1fe.0000.2028,4028 */
- u_int64_t pad12[251];
+ u_int64_t pad11[250];
/* This is really the IOMMU's, not the PCI bus's */
struct iommu_strbuf pci_strbuf; /* 1fe.0000.2800-210 */
#define psy_iommu_strbuf psy_pcictl[0].pci_strbuf
- u_int64_t pad13[765];
+ u_int64_t pad12[765];
} psy_pcictl[2]; /* For PCI a and b */
/* NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 1fe.0000.8000 respectively */
- u_int64_t pad14[2048];
+ u_int64_t pad13[2048];
u_int64_t dma_scb_diag0; /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */
u_int64_t dma_scb_diag1; /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */
- u_int64_t pad15[126];
+ u_int64_t pad14[126];
u_int64_t iommu_svadiag; /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */
u_int64_t iommu_tlb_comp_diag; /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */
- u_int64_t pad16[30];
+ u_int64_t pad15[30];
u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */
u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */
u_int64_t tlb_data_diag[16]; /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */
- u_int64_t pad17[48];
+ u_int64_t pad16[48];
u_int64_t pci_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.a800 */
u_int64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */
- u_int64_t pad18[254];
+ u_int64_t pad17[254];
struct strbuf_diag {
u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */
u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */
u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */
- u_int64_t pad19[16];
+ u_int64_t pad18[16];
u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */
- u_int64_t pad20[208];
+ u_int64_t pad19[208];
} psy_strbufdiag[2]; /* For PCI a and b */
/*
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