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[src/trunk]: src/sys/arch Move arm32 ports over to using <arm/armreg.h>, so <...
details: https://anonhg.NetBSD.org/src/rev/64655d16bc8e
branches: trunk
changeset: 504246:64655d16bc8e
user: bjh21 <bjh21%NetBSD.org@localhost>
date: Sun Feb 25 21:31:13 2001 +0000
description:
Move arm32 ports over to using <arm/armreg.h>, so <cpu.h> mostly contains
NetBSD-specific definitions.
This also entails some changes to the way CPU identification is done. I hope
I've got it right.
diffstat:
sys/arch/arm/include/cpu.h | 109 +--------------------------
sys/arch/arm/mainbus/cpu.c | 38 ++++----
sys/arch/arm32/arm32/cpufunc.c | 15 ++-
sys/arch/arm32/arm32/db_trace.c | 4 +-
sys/arch/arm32/footbridge/footbridge.c | 4 +-
sys/arch/arm32/footbridge/footbridge_clock.c | 4 +-
sys/arch/arm32/iomd/iomd_clock.c | 4 +-
sys/arch/arm32/ofw/ofwgencfg_clock.c | 4 +-
sys/arch/arm32/riscpc/rpc_machdep.c | 6 +-
sys/arch/hpcarm/hpcarm/cpufunc.c | 6 +-
sys/arch/hpcarm/hpcarm/db_trace.c | 4 +-
sys/arch/hpcarm/hpcarm/hpc_machdep.c | 4 +-
12 files changed, 51 insertions(+), 151 deletions(-)
diffs (truncated from 432 to 300 lines):
diff -r bce05eee23d3 -r 64655d16bc8e sys/arch/arm/include/cpu.h
--- a/sys/arch/arm/include/cpu.h Sun Feb 25 20:41:43 2001 +0000
+++ b/sys/arch/arm/include/cpu.h Sun Feb 25 21:31:13 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.2 2001/02/25 17:04:54 bjh21 Exp $ */
+/* $NetBSD: cpu.h,v 1.3 2001/02/25 21:31:13 bjh21 Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@@ -62,6 +62,8 @@
#error "option CPU_ARM7 is required with CPU_ARM7500"
#endif
+#include <arm/armreg.h>
+
#ifdef CPU_ARM7500
#ifdef CPU_ARM6
#error "CPU options CPU_ARM6 and CPU_ARM7500 are not compatible"
@@ -74,111 +76,6 @@
#endif
#endif /* CPU_ARM7500 */
-/*
- * ARM Process Status Register
- *
- * The picture in the ARM manuals looks like this:
- * 3 3 2 2 2
- * 1 0 9 8 7 8 7 6 5 4 0
- * +-------+---------------------------------------+-+-+-+---------+
- * | flags | reserved |I|F| |M M M M M|
- * |n z c v| | | | |4 3 2 1 0|
- * +-------+---------------------------------------+-+-+-+---------+
- */
-
-#define PSR_FLAGS 0xf0000000 /* flags */
-#define PSR_N_bit (1 << 31) /* negative */
-#define PSR_Z_bit (1 << 30) /* zero */
-#define PSR_C_bit (1 << 29) /* carry */
-#define PSR_V_bit (1 << 28) /* overflow */
-
-#define I32_bit (1 << 7) /* IRQ disable */
-#define F32_bit (1 << 6) /* FIQ disable */
-
-#define PSR_MODE 0x0000001f /* mode mask */
-#define PSR_USR32_MODE 0x00000010
-#define PSR_FIQ32_MODE 0x00000011
-#define PSR_IRQ32_MODE 0x00000012
-#define PSR_SVC32_MODE 0x00000013
-#define PSR_ABT32_MODE 0x00000017
-#define PSR_UND32_MODE 0x0000001b
-#define PSR_32_MODE 0x00000010
-
-#define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
-#define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
-
-/*
- * ARM Instructions
- *
- * 3 3 2 2 2
- * 1 0 9 8 7 0
- * +-------+-------------------------------------------------------+
- * | cond | instruction dependant |
- * |c c c c| |
- * +-------+-------------------------------------------------------+
- */
-
-#define INSN_SIZE 4 /* Always 4 bytes */
-#define INSN_COND_MASK 0xf0000000 /* Condition mask */
-#define INSN_COND_AL 0xe0000000 /* Always condition */
-
-/* Some of the definitions below need cleaning up for V3/V4 architectures */
-
-#define CPU_ID_DESIGNER_MASK 0xff000000
-#define CPU_ID_ARM_LTD 0x41000000
-#define CPU_ID_DEC 0x44000000
-#define CPU_ID_TYPE_MASK 0x00ff0000
-#define CPU_ID_ARM 0x00560000
-#define CPU_ID_ARM7500 0x00020000
-#define CPU_ID_CPU_MASK 0x0000fff0
-#define ID_ARM610 0x00000610
-#define ID_ARM700 0x00007000
-#define ID_ARM710 0x00007100
-#define ID_ARM810 0x00008100
-#define ID_SA110 0x0000a100
-#define ID_SA1100 0x0000a110
-#define ID_SA1110 0x0000b110
-
-#define CPU_ID_REVISION_MASK 0x0000000f
-
-#define CPU_CONTROL_MMU_ENABLE 0x0001
-#define CPU_CONTROL_AFLT_ENABLE 0x0002
-#define CPU_CONTROL_DC_ENABLE 0x0004
-#define CPU_CONTROL_WBUF_ENABLE 0x0008
-#define CPU_CONTROL_32BP_ENABLE 0x0010
-#define CPU_CONTROL_32BD_ENABLE 0x0020
-#define CPU_CONTROL_LABT_ENABLE 0x0040
-#define CPU_CONTROL_BEND_ENABLE 0x0080
-#define CPU_CONTROL_SYST_ENABLE 0x0100
-#define CPU_CONTROL_ROM_ENABLE 0x0200
-#define CPU_CONTROL_CPCLK 0x0400
-#define CPU_CONTROL_BPRD_ENABLE 0x0800
-#define CPU_CONTROL_IC_ENABLE 0x1000
-
-#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
-
-/* Fault status register definitions */
-
-#define FAULT_TYPE_MASK 0x0f
-#define FAULT_USER 0x10
-
-#define FAULT_WRTBUF_0 0x00
-#define FAULT_WRTBUF_1 0x02
-#define FAULT_BUSERR_0 0x04
-#define FAULT_BUSERR_1 0x06
-#define FAULT_BUSERR_2 0x08
-#define FAULT_BUSERR_3 0x0a
-#define FAULT_ALIGN_0 0x01
-#define FAULT_ALIGN_1 0x03
-#define FAULT_BUSTRNL1 0x0c
-#define FAULT_BUSTRNL2 0x0e
-#define FAULT_TRANS_S 0x05
-#define FAULT_TRANS_P 0x07
-#define FAULT_DOMAIN_S 0x09
-#define FAULT_DOMAIN_P 0x0b
-#define FAULT_PERM_S 0x0d
-#define FAULT_PERM_P 0x0f
-
#ifdef _LOCORE
#define IRQdisable \
stmfd sp!, {r0} ; \
diff -r bce05eee23d3 -r 64655d16bc8e sys/arch/arm/mainbus/cpu.c
--- a/sys/arch/arm/mainbus/cpu.c Sun Feb 25 20:41:43 2001 +0000
+++ b/sys/arch/arm/mainbus/cpu.c Sun Feb 25 21:31:13 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.2 2001/02/25 18:40:26 bjh21 Exp $ */
+/* $NetBSD: cpu.c,v 1.3 2001/02/25 21:31:14 bjh21 Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -200,7 +200,7 @@
#ifdef CPU_ARM8
if (cpus[CPU_MASTER].cpu_class == CPU_CLASS_ARM
- && (cpus[CPU_MASTER].cpu_id & CPU_ID_CPU_MASK) == ID_ARM810) {
+ && (cpus[CPU_MASTER].cpu_id & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
int clock = arm8_clock_config(0, 0);
char *fclk;
printf("%s: ARM810 cp15=%02x", dev_name, clock);
@@ -341,41 +341,41 @@
return;
}
-/* if ((cpuid & CPU_ID_DESIGNER_MASK) != CPU_ID_ARM_LTD)
- printf("Unrecognised designer ID = %08x\n", cpuid);*/
-
switch (cpuid & CPU_ID_CPU_MASK) {
#ifdef CPU_ARM6
- case ID_ARM610:
- cpu_type = cpuid & CPU_ID_CPU_MASK;
+ case CPU_ID_ARM610:
+ cpu_type = cpuid & CPU_ID_PARTNO_MASK;
break;
#endif
#ifdef CPU_ARM7
- case ID_ARM710 :
- case ID_ARM700 :
- cpu_type = (cpuid & CPU_ID_CPU_MASK) >> 4;
+ case CPU_ID_ARM700 :
+ case CPU_ID_ARM710 :
+ case CPU_ID_ARM7500:
+ case CPU_ID_ARM7100:
+ case CPU_ID_ARM710T:
+ cpu_type = (cpuid & CPU_ID_PARTNO_MASK) >> 4;
break;
#endif
#ifdef CPU_ARM8
- case ID_ARM810 :
- cpu_type = (cpuid & CPU_ID_CPU_MASK) >> 4;
+ case CPU_ID_ARM810 :
+ cpu_type = (cpuid & CPU_ID_PARTNO_MASK) >> 4;
break;
#endif
#ifdef CPU_SA110
- case ID_SA110 :
- cpu_type = (cpuid & CPU_ID_CPU_MASK) >> 4;
+ case CPU_ID_SA110 :
+ cpu_type = (cpuid & CPU_ID_PARTNO_MASK) >> 4;
cpu->cpu_class = CPU_CLASS_SARM;
sprintf(cpu->cpu_model, "SA-110 rev %d",
cpuid & CPU_ID_REVISION_MASK);
break;
- case ID_SA1100 :
- cpu_type = (cpuid & CPU_ID_CPU_MASK) >> 4;
+ case CPU_ID_SA1100 :
+ cpu_type = (cpuid & CPU_ID_PARTNO_MASK) >> 4;
cpu->cpu_class = CPU_CLASS_SARM;
sprintf(cpu->cpu_model, "SA-1100 rev %d",
cpuid & CPU_ID_REVISION_MASK);
break;
- case ID_SA1110 :
- cpu_type = (cpuid & CPU_ID_CPU_MASK) >> 4;
+ case CPU_ID_SA1110 :
+ cpu_type = (cpuid & CPU_ID_PARTNO_MASK) >> 4;
cpu->cpu_class = CPU_CLASS_SARM;
sprintf(cpu->cpu_model, "SA-1110 rev %d",
cpuid & CPU_ID_REVISION_MASK);
@@ -383,7 +383,7 @@
#endif
default :
printf("Unrecognised processor ID = %08x\n", cpuid);
- cpu_type = cpuid & CPU_ID_CPU_MASK;
+ cpu_type = cpuid & CPU_ID_PARTNO_MASK;
break;
}
diff -r bce05eee23d3 -r 64655d16bc8e sys/arch/arm32/arm32/cpufunc.c
--- a/sys/arch/arm32/arm32/cpufunc.c Sun Feb 25 20:41:43 2001 +0000
+++ b/sys/arch/arm32/arm32/cpufunc.c Sun Feb 25 21:31:13 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.12 2001/02/18 12:42:31 reinoud Exp $ */
+/* $NetBSD: cpufunc.c,v 1.13 2001/02/25 21:31:14 bjh21 Exp $ */
/*
* arm8 support code Copyright (c) 1997 ARM Limited
@@ -353,26 +353,29 @@
switch (cputype) {
#ifdef CPU_ARM6
- case ID_ARM610:
+ case CPU_ID_ARM610:
cpufuncs = arm6_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 0;
break;
#endif /* CPU_ARM6 */
#ifdef CPU_ARM7
- case ID_ARM700:
- case ID_ARM710:
+ case CPU_ID_ARM700:
+ case CPU_ID_ARM710:
+ case CPU_ID_ARM7500:
+ case CPU_ID_ARM7100:
+ case CPU_ID_ARM710T:
cpufuncs = arm7_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 0;
break;
#endif /* CPU_ARM7 */
#ifdef CPU_ARM8
- case ID_ARM810:
+ case CPU_ID_ARM810:
cpufuncs = arm8_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
break;
#endif /* CPU_ARM8 */
#ifdef CPU_SA110
- case ID_SA110:
+ case CPU_ID_SA110:
cpufuncs = sa110_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
break;
diff -r bce05eee23d3 -r 64655d16bc8e sys/arch/arm32/arm32/db_trace.c
--- a/sys/arch/arm32/arm32/db_trace.c Sun Feb 25 20:41:43 2001 +0000
+++ b/sys/arch/arm32/arm32/db_trace.c Sun Feb 25 21:31:13 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: db_trace.c,v 1.13 2000/05/26 03:34:26 jhawk Exp $ */
+/* $NetBSD: db_trace.c,v 1.14 2001/02/25 21:31:14 bjh21 Exp $ */
/*
* Copyright (c) 1996 Scott K. Stevens
@@ -103,7 +103,7 @@
pc = frame->fr_pc;
/* Adjust the PC so the same address is printed no matter what CPU */
- if (cputype == ID_SA110 || cputype == ID_ARM810)
+ if (cputype == CPU_ID_SA110 || cputype == CPU_ID_ARM810)
pc += 4;
if (!INKERNEL(pc))
break;
diff -r bce05eee23d3 -r 64655d16bc8e sys/arch/arm32/footbridge/footbridge.c
--- a/sys/arch/arm32/footbridge/footbridge.c Sun Feb 25 20:41:43 2001 +0000
+++ b/sys/arch/arm32/footbridge/footbridge.c Sun Feb 25 21:31:13 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: footbridge.c,v 1.4 2000/02/13 05:00:57 mark Exp $ */
+/* $NetBSD: footbridge.c,v 1.5 2001/02/25 21:31:14 bjh21 Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@@ -230,7 +230,7 @@
/* Setup fast SA110 cache clean area */
#ifdef CPU_SA110
- if (cputype == ID_SA110)
+ if (cputype == CPU_ID_SA110)
footbridge_sa110_cc_setup();
#endif /* CPU_SA110 */
diff -r bce05eee23d3 -r 64655d16bc8e sys/arch/arm32/footbridge/footbridge_clock.c
--- a/sys/arch/arm32/footbridge/footbridge_clock.c Sun Feb 25 20:41:43 2001 +0000
+++ b/sys/arch/arm32/footbridge/footbridge_clock.c Sun Feb 25 21:31:13 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: footbridge_clock.c,v 1.5 2000/12/12 06:06:05 mycroft Exp $ */
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