[src/trunk]: src/sys/dev/pci Check and set PCI power management register. cl...

[tacha <tacha%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8a1451f0a4cd
branches:  trunk
changeset: 503780:8a1451f0a4cd
user:      tacha <tacha%NetBSD.org@localhost>
date:      Tue Feb 13 04:11:11 2001 +0000

description:
Check and set PCI power management register.  clcs now works when
warm boot from Windows.

diffstat:

 sys/dev/pci/cs4280.c |  24 ++++++++++++++++++++----
 1 files changed, 20 insertions(+), 4 deletions(-)

diffs (50 lines):

diff -r 1b0e44bca51a -r 8a1451f0a4cd sys/dev/pci/cs4280.c
--- a/sys/dev/pci/cs4280.c      Tue Feb 13 03:11:26 2001 +0000
+++ b/sys/dev/pci/cs4280.c      Tue Feb 13 04:11:11 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cs4280.c,v 1.14 2001/02/07 14:41:10 tacha Exp $        */
+/*     $NetBSD: cs4280.c,v 1.15 2001/02/13 04:11:11 tacha Exp $        */
 
 /*
  * Copyright (c) 1999, 2000 Tatoku Ogaito.  All rights reserved.
@@ -208,10 +208,11 @@
        pci_chipset_tag_t pc = pa->pa_pc;
        char const *intrstr;
        pci_intr_handle_t ih;
-       pcireg_t csr;
+       pcireg_t reg;
        char devinfo[256];
        mixer_ctrl_t ctl;
        u_int32_t mem;
+       int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg;
 
        pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
        printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
@@ -232,10 +233,25 @@
 
        sc->sc_dmatag = pa->pa_dmat;
 
+       /* Check and set Power State */
+       if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT,
+           &pci_pwrmgmt_cap_reg, 0)) {
+               pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4;
+               reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+                   pci_pwrmgmt_csr_reg);
+               DPRINTF(("%s: Power State is %d\n", 
+                   sc->sc_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK));
+               if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) {
+                       pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg,
+                           (reg & ~PCI_PMCSR_STATE_MASK) |
+                           PCI_PMCSR_STATE_D0);
+               }
+       }
+
        /* Enable the device (set bus master flag) */
-       csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+       reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
        pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
-                      csr | PCI_COMMAND_MASTER_ENABLE);
+                      reg | PCI_COMMAND_MASTER_ENABLE);
 
        /* LATENCY_TIMER setting */
        mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);