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[src/trunk]: src/sys/dev/pci Add support for the Promise Ultra/33 and /66 pci...
details: https://anonhg.NetBSD.org/src/rev/d312c54d8678
branches: trunk
changeset: 475889:d312c54d8678
user: bouyer <bouyer%NetBSD.org@localhost>
date: Sun Aug 29 17:20:10 1999 +0000
description:
Add support for the Promise Ultra/33 and /66 pci IDE controller. In addition to
chip-dependant code this required the following changes:
- Instead of attaching the device in a generic way with some chip-dependant
routines, use a chip-dependant attach routine with some common code
factored out. The code is marginally bigger, but this allows the CMD64x
flag hack to go away.
- For chips that report per-channel 'irq triggered', test this before calling
wdcintr() for the native-pci irq case (compat intr can't be shared),
as wdcintr() has no good way to know if a irq was for it or not, and
ends up with irq loss. XXX for chips that don't have this feature irq sharing
will not work properly !
- add my copyrigth notice (could have been done some time ago I think :)
There are still some issues to be solved with the Promise controller and
ATAPI devices.
Many thanks to Paul Newhouse for shipping me 2 Ultra/33 boards for doing this
work.
diffstat:
sys/dev/pci/pciide.c | 1605 ++++++++++++++++++++++--------------
sys/dev/pci/pciide_acer_reg.h | 7 +-
sys/dev/pci/pciide_cmd_reg.h | 7 +-
sys/dev/pci/pciide_pdc202xx_reg.h | 102 ++
4 files changed, 1111 insertions(+), 610 deletions(-)
diffs (truncated from 2235 to 300 lines):
diff -r a391cca3650a -r d312c54d8678 sys/dev/pci/pciide.c
--- a/sys/dev/pci/pciide.c Sun Aug 29 17:06:43 1999 +0000
+++ b/sys/dev/pci/pciide.c Sun Aug 29 17:20:10 1999 +0000
@@ -1,4 +1,39 @@
-/* $NetBSD: pciide.c,v 1.40 1999/07/12 13:49:38 bouyer Exp $ */
+/* $NetBSD: pciide.c,v 1.41 1999/08/29 17:20:10 bouyer Exp $ */
+
+
+/*
+ * Copyright (c) 1999 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -77,6 +112,7 @@
#include <dev/pci/pciide_cy693_reg.h>
#include <dev/pci/pciide_sis_reg.h>
#include <dev/pci/pciide_acer_reg.h>
+#include <dev/pci/pciide_pdc202xx_reg.h>
#include <dev/ata/atavar.h>
#include <dev/ic/wdcreg.h>
#include <dev/ic/wdcvar.h>
@@ -151,46 +187,39 @@
} pciide_channels[PCIIDE_NUM_CHANNELS];
};
-void default_setup_cap __P((struct pciide_softc*));
-void default_setup_chip __P((struct pciide_softc*));
-void default_channel_map __P((struct pci_attach_args *,
- struct pciide_channel *));
+void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
-void piix_setup_cap __P((struct pciide_softc*));
-void piix_setup_chip __P((struct pciide_softc*));
+void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+void piix_channel_map __P((struct pci_attach_args *, struct pciide_channel *));
void piix_setup_channel __P((struct channel_softc*));
-void piix3_4_setup_chip __P((struct pciide_softc*));
void piix3_4_setup_channel __P((struct channel_softc*));
-void piix_channel_map __P((struct pci_attach_args *, struct pciide_channel *));
static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t));
static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*));
static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t));
-void apollo_setup_cap __P((struct pciide_softc*));
-void apollo_setup_chip __P((struct pciide_softc*));
+void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void apollo_setup_channel __P((struct channel_softc*));
-void apollo_channel_map __P((struct pci_attach_args *,
- struct pciide_channel *));
-void cmd0643_6_setup_cap __P((struct pciide_softc*));
-void cmd0643_6_setup_chip __P((struct pciide_softc*));
+void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void cmd0643_6_setup_channel __P((struct channel_softc*));
-void cmd_channel_map __P((struct pci_attach_args *, struct pciide_channel *));
+void cmd_channel_map __P((struct pci_attach_args *,
+ struct pciide_softc *, int));
+int cmd_pci_intr __P((void *));
-void cy693_setup_cap __P((struct pciide_softc*));
-void cy693_setup_chip __P((struct pciide_softc*));
+void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void cy693_setup_channel __P((struct channel_softc*));
-void cy693_channel_map __P((struct pci_attach_args *, struct pciide_channel *));
+
+void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+void sis_setup_channel __P((struct channel_softc*));
-void sis_setup_cap __P((struct pciide_softc*));
-void sis_setup_chip __P((struct pciide_softc*));
-void sis_setup_channel __P((struct channel_softc*));
-void sis_channel_map __P((struct pci_attach_args *, struct pciide_channel *));
+void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+void acer_setup_channel __P((struct channel_softc*));
+int acer_pci_intr __P((void *));
-void acer_setup_cap __P((struct pciide_softc*));
-void acer_setup_chip __P((struct pciide_softc*));
-void acer_setup_channel __P((struct channel_softc*));
-void acer_channel_map __P((struct pci_attach_args *, struct pciide_channel *));
+void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+void pdc202xx_setup_channel __P((struct channel_softc*));
+int pdc202xx_pci_intr __P((void *));
void pciide_channel_dma_setup __P((struct pciide_channel *));
int pciide_dma_table_setup __P((struct pciide_softc*, int, int));
@@ -202,100 +231,67 @@
struct pciide_product_desc {
u_int32_t ide_product;
int ide_flags;
- int ide_num_channels;
const char *ide_name;
- /* init controller's capabilities for drives probe */
- void (*setup_cap) __P((struct pciide_softc*));
- /* init controller after drives probe */
- void (*setup_chip) __P((struct pciide_softc*));
- /* map channel if possible/necessary */
- void (*channel_map) __P((struct pci_attach_args *,
- struct pciide_channel *));
+ /* map and setup chip, probe drives */
+ void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*));
};
/* Flags for ide_flags */
-#define CMD_PCI064x_IOEN 0x01 /* CMD-style PCI_COMMAND_IO_ENABLE */
-#define ONE_QUEUE 0x02 /* device need serialised access */
+#define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */
/* Default product description for devices not known from this controller */
const struct pciide_product_desc default_product_desc = {
0,
0,
- PCIIDE_NUM_CHANNELS,
"Generic PCI IDE controller",
- default_setup_cap,
- default_setup_chip,
- default_channel_map
+ default_chip_map,
};
const struct pciide_product_desc pciide_intel_products[] = {
{ PCI_PRODUCT_INTEL_82092AA,
0,
- PCIIDE_NUM_CHANNELS,
"Intel 82092AA IDE controller",
- default_setup_cap,
- default_setup_chip,
- default_channel_map
+ default_chip_map,
},
{ PCI_PRODUCT_INTEL_82371FB_IDE,
0,
- PCIIDE_NUM_CHANNELS,
"Intel 82371FB IDE controller (PIIX)",
- piix_setup_cap,
- piix_setup_chip,
- piix_channel_map
+ piix_chip_map,
},
{ PCI_PRODUCT_INTEL_82371SB_IDE,
0,
- PCIIDE_NUM_CHANNELS,
"Intel 82371SB IDE Interface (PIIX3)",
- piix_setup_cap,
- piix3_4_setup_chip,
- piix_channel_map
+ piix_chip_map,
},
{ PCI_PRODUCT_INTEL_82371AB_IDE,
0,
- PCIIDE_NUM_CHANNELS,
"Intel 82371AB IDE controller (PIIX4)",
- piix_setup_cap,
- piix3_4_setup_chip,
- piix_channel_map
+ piix_chip_map,
},
{ 0,
0,
- 0,
NULL,
}
};
const struct pciide_product_desc pciide_cmd_products[] = {
{ PCI_PRODUCT_CMDTECH_640,
- ONE_QUEUE | CMD_PCI064x_IOEN,
- PCIIDE_NUM_CHANNELS,
+ 0,
"CMD Technology PCI0640",
- default_setup_cap,
- default_setup_chip,
- cmd_channel_map
+ cmd_chip_map
},
{ PCI_PRODUCT_CMDTECH_643,
- ONE_QUEUE | CMD_PCI064x_IOEN,
- PCIIDE_NUM_CHANNELS,
+ 0,
"CMD Technology PCI0643",
- cmd0643_6_setup_cap,
- cmd0643_6_setup_chip,
- cmd_channel_map
+ cmd0643_6_chip_map,
},
{ PCI_PRODUCT_CMDTECH_646,
- ONE_QUEUE | CMD_PCI064x_IOEN,
- PCIIDE_NUM_CHANNELS,
+ 0,
"CMD Technology PCI0646",
- cmd0643_6_setup_cap,
- cmd0643_6_setup_chip,
- cmd_channel_map
+ cmd0643_6_chip_map,
},
{ 0,
0,
- 0,
NULL,
}
};
@@ -303,23 +299,16 @@
const struct pciide_product_desc pciide_via_products[] = {
{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
0,
- PCIIDE_NUM_CHANNELS,
"VIA Technologies VT82C586 (Apollo VP) IDE Controller",
- apollo_setup_cap,
- apollo_setup_chip,
- apollo_channel_map
+ apollo_chip_map,
},
{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
0,
- PCIIDE_NUM_CHANNELS,
"VIA Technologies VT82C586A IDE Controller",
- apollo_setup_cap,
- apollo_setup_chip,
- apollo_channel_map
+ apollo_chip_map,
},
{ 0,
0,
- 0,
NULL,
}
};
@@ -327,15 +316,11 @@
const struct pciide_product_desc pciide_cypress_products[] = {
{ PCI_PRODUCT_CONTAQ_82C693,
0,
- 1,
"Contaq Microsystems CY82C693 IDE Controller",
- cy693_setup_cap,
- cy693_setup_chip,
- cy693_channel_map
+ cy693_chip_map,
},
{ 0,
0,
- 0,
NULL,
}
};
@@ -343,15 +328,11 @@
const struct pciide_product_desc pciide_sis_products[] = {
{ PCI_PRODUCT_SIS_5597_IDE,
0,
- PCIIDE_NUM_CHANNELS,
"Silicon Integrated System 5597/5598 IDE controller",
- sis_setup_cap,
- sis_setup_chip,
- sis_channel_map
+ sis_chip_map,
},
{ 0,
0,
- 0,
NULL,
}
};
@@ -359,14 +340,27 @@
const struct pciide_product_desc pciide_acer_products[] = {
{ PCI_PRODUCT_ALI_M5229,
0,
- PCIIDE_NUM_CHANNELS,
"Acer Labs M5229 UDMA IDE Controller",
- acer_setup_cap,
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