[src/trunk]: src/sys/arch/sparc64/sparc64 Fixup counter-timer interrupt lossage.

[eeh <eeh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c77ea7b3609d
branches:  trunk
changeset: 494446:c77ea7b3609d
user:      eeh <eeh%NetBSD.org@localhost>
date:      Thu Jul 06 14:13:05 2000 +0000

description:
Fixup counter-timer interrupt lossage.

diffstat:

 sys/arch/sparc64/sparc64/clock.c |  86 +++++++--------------------------------
 1 files changed, 17 insertions(+), 69 deletions(-)

diffs (144 lines):

diff -r c7afce2fa574 -r c77ea7b3609d sys/arch/sparc64/sparc64/clock.c
--- a/sys/arch/sparc64/sparc64/clock.c  Thu Jul 06 14:12:31 2000 +0000
+++ b/sys/arch/sparc64/sparc64/clock.c  Thu Jul 06 14:13:05 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: clock.c,v 1.22 2000/06/29 07:37:57 mrg Exp $ */
+/*     $NetBSD: clock.c,v 1.23 2000/07/06 14:13:05 eeh Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -106,20 +106,6 @@
 
 extern struct idprom idprom;
 
-#define intersil_command(run, interrupt) \
-    (run | interrupt | INTERSIL_CMD_FREQ_32K | INTERSIL_CMD_24HR_MODE | \
-     INTERSIL_CMD_NORMAL_MODE)
-
-#define intersil_disable(CLOCK) \
-    CLOCK->clk_cmd_reg = \
-    intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE)
-
-#define intersil_enable(CLOCK) \
-    CLOCK->clk_cmd_reg = \
-    intersil_command(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE)
-
-#define intersil_clear(CLOCK) CLOCK->clk_intr_reg
-
 static long tick_increment;
 
 static struct intrhand level10 = { clockintr };
@@ -350,10 +336,11 @@
 
        /* Install the appropriate interrupt vector here */
        level10.ih_number = ma->ma_interrupts[0];
-/*     level10.ih_clr = (void*)timerreg_4u.t_clrintr[0]; */
+       level10.ih_clr = (void*)&timerreg_4u.t_clrintr[0];
        intr_establish(10, &level10);
        level14.ih_number = ma->ma_interrupts[1];
-/*     level14.ih_clr = (void*)timerreg_4u.t_clrintr[1]; */
+       level14.ih_clr = (void*)&timerreg_4u.t_clrintr[1];
+
        intr_establish(14, &level14);
        printf(" irq vectors %lx and %lx", 
               (u_long)level10.ih_number, 
@@ -570,24 +557,23 @@
         * Also need to map the interrupts cause we're not a child of the sbus.
         * N.B. By default timer[0] is disabled and timer[1] is enabled.
         */
-#if 0
-       timerreg_4u.t_timer[0].t_limit = tmr_ustolim(tick)|TMR_LIM_IEN|TMR_LIM_PERIODIC|TMR_LIM_RELOAD;
-       timerreg_4u.t_mapintr[0] |= INTMAP_V; 
-       timerreg_4u.t_timer[1].t_limit = tmr_ustolim(statint)|TMR_LIM_IEN|TMR_LIM_RELOAD;
-       timerreg_4u.t_mapintr[1] |= INTMAP_V; 
-#else
-       stxa(&timerreg_4u.t_timer[0].t_limit, ASI_NUCLEUS, tmr_ustolim(tick)|TMR_LIM_IEN|TMR_LIM_PERIODIC|TMR_LIM_RELOAD); 
-       stxa(&timerreg_4u.t_mapintr[0], ASI_NUCLEUS, timerreg_4u.t_mapintr[0]|INTMAP_V); 
+       stxa((vaddr_t)&timerreg_4u.t_timer[0].t_limit, ASI_NUCLEUS,
+            tmr_ustolim(tick)|TMR_LIM_IEN|TMR_LIM_PERIODIC|TMR_LIM_RELOAD); 
+       stxa((vaddr_t)&timerreg_4u.t_mapintr[0], ASI_NUCLEUS, 
+            timerreg_4u.t_mapintr[0]|INTMAP_V); 
 
 #ifdef DEBUG
        if (intrdebug)
                /* Neglect to enable timer */
-               stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(statint)|TMR_LIM_RELOAD); 
+               stxa((vaddr_t)&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, 
+                    tmr_ustolim(statint)|TMR_LIM_RELOAD); 
        else
 #endif
-               stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(statint)|TMR_LIM_IEN|TMR_LIM_RELOAD); 
-       stxa(&timerreg_4u.t_mapintr[1], ASI_NUCLEUS, timerreg_4u.t_mapintr[1]|INTMAP_V); 
-#endif
+               stxa((vaddr_t)&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, 
+                    tmr_ustolim(statint)|TMR_LIM_IEN|TMR_LIM_RELOAD); 
+       stxa((vaddr_t)&timerreg_4u.t_mapintr[1], ASI_NUCLEUS, 
+            timerreg_4u.t_mapintr[1]|INTMAP_V); 
+
        statmin = statint - (statvar >> 1);
        
        /* Also zero out %tick which should be valid for at least 10 years */
@@ -614,27 +600,7 @@
 clockintr(cap)
        void *cap;
 {
-       int s;
-
-#if 1
        /* Let locore.s clear the interrupt for us. */
-       /*
-        * Protect the clearing of the clock interrupt.  If we don't
-        * do this, and we're interrupted (by the zs, for example),
-        * the clock stops!
-        * XXX WHY DOES THIS HAPPEN?
-        */
-       s = splhigh();
-
-       /* read the register to clear the interrupt */
-#if 0
-       timerreg_4u.t_clrintr[0] = 0;
-#else
-       stxa(&timerreg_4u.t_clrintr[0], ASI_NUCLEUS, 0LL);
-#endif
-       splx(s);
-#endif
-
        hardclock((struct clockframe *)cap);
        return (1);
 }
@@ -688,15 +654,6 @@
 #ifdef NOT_DEBUG
        prom_printf("!");
 #endif
-#if 1
-       /* Let locore.s clear the interrupt for us. */
-       /* read the limit register to clear the interrupt */
-#if 0
-       timerreg_4u.t_clrintr[1]=0;
-#else
-       stxa(&timerreg_4u.t_clrintr[1], ASI_NUCLEUS, 0LL);
-#endif
-#endif
        statclock((struct clockframe *)cap);
 #ifdef NOTDEF_DEBUG
        /* Don't re-schedule the IRQ */
@@ -713,17 +670,8 @@
        } while (r == 0);
        newint = statmin + r;
 
-#if 0
-       timerreg_4u.t_timer[1].t_limit = tmr_ustolim(newint)|TMR_LIM_IEN|TMR_LIM_RELOAD;
-#else
-       stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(newint)|TMR_LIM_IEN|TMR_LIM_RELOAD);
-
-#ifdef NOT_DEBUG
-       /* Use normal clock instead */
-       stathz = 0;
-       stxa(&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, tmr_ustolim(newint)|TMR_LIM_RELOAD);
-#endif
-#endif
+       stxa((vaddr_t)&timerreg_4u.t_timer[1].t_limit, ASI_NUCLEUS, 
+            tmr_ustolim(newint)|TMR_LIM_IEN|TMR_LIM_RELOAD);
        return (1);
 }