[src/trunk]: src/lib/libarch/arm Correct spelling of 'synchronized'.

[wiz <wiz%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/64cdaaf8ffb2
branches:  trunk
changeset: 537528:64cdaaf8ffb2
user:      wiz <wiz%NetBSD.org@localhost>
date:      Wed Oct 02 10:34:23 2002 +0000

description:
Correct spelling of 'synchronized'.

diffstat:

 lib/libarch/arm/arm_sync_icache.2 |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (33 lines):

diff -r 977a8dd80da9 -r 64cdaaf8ffb2 lib/libarch/arm/arm_sync_icache.2
--- a/lib/libarch/arm/arm_sync_icache.2 Wed Oct 02 10:09:51 2002 +0000
+++ b/lib/libarch/arm/arm_sync_icache.2 Wed Oct 02 10:34:23 2002 +0000
@@ -1,4 +1,4 @@
-.\"    $NetBSD: arm_sync_icache.2,v 1.2 2002/10/01 15:58:37 wiz Exp $
+.\"    $NetBSD: arm_sync_icache.2,v 1.3 2002/10/02 10:34:23 wiz Exp $
 .\"
 .\" Copyright (c) 1996 Mark Brinicombe
 .\" All rights reserved.
@@ -45,12 +45,12 @@
 .Sh DESCRIPTION
 .Fn arm_sync_icache
 will make sure that all the entries in the processor instruction cache
-are synchorised with main memory and that any data in a write back cache
+are synchronized with main memory and that any data in a write back cache
 has been cleaned.
 Some ARM processors (e.g. SA110) have separate instruction and data
 caches thus any dynamically generated or modified code needs to be
 written back from any data caches to main memory and the instruction
-cache needs to be synchronised with main memory.
+cache needs to be synchronized with main memory.
 .Pp
 On such processors
 .Fn arm_sync_icache
@@ -63,7 +63,7 @@
 .Fa addr
 and a length
 .Fa len
-to describe the area of memory that needs to be cleaned and synchronised.
+to describe the area of memory that needs to be cleaned and synchronized.
 .Sh ERRORS
 .Fn arm_sync_icache
 will never fail so will always return 0.