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[src/trunk]: src/sys/arch/amiga Switch to cacheops. This closes PR 1960.
details: https://anonhg.NetBSD.org/src/rev/b5bba86b8841
branches: trunk
changeset: 476116:b5bba86b8841
user: is <is%NetBSD.org@localhost>
date: Mon Sep 06 21:50:47 1999 +0000
description:
Switch to cacheops. This closes PR 1960.
diffstat:
sys/arch/amiga/amiga/db_memrw.c | 4 +-
sys/arch/amiga/amiga/locore.s | 181 +------------------------------------
sys/arch/amiga/amiga/pmap.c | 5 +-
sys/arch/amiga/amiga/sys_machdep.c | 7 +-
sys/arch/amiga/amiga/trap.c | 3 +-
sys/arch/amiga/amiga/vm_machdep.c | 3 +-
sys/arch/amiga/conf/files.amiga | 4 +-
sys/arch/amiga/dev/siop.c | 5 +-
8 files changed, 26 insertions(+), 186 deletions(-)
diffs (truncated from 359 to 300 lines):
diff -r da98c358cb9f -r b5bba86b8841 sys/arch/amiga/amiga/db_memrw.c
--- a/sys/arch/amiga/amiga/db_memrw.c Mon Sep 06 21:50:39 1999 +0000
+++ b/sys/arch/amiga/amiga/db_memrw.c Mon Sep 06 21:50:47 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: db_memrw.c,v 1.8 1997/10/09 07:35:04 jtc Exp $ */
+/* $NetBSD: db_memrw.c,v 1.9 1999/09/06 21:50:47 is Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@@ -55,6 +55,8 @@
#include <machine/cpu.h>
#include <machine/pte.h>
+#include <m68k/cacheops.h>
+
static char db_read_data __P((char *src));
void db_read_bytes __P((vm_offset_t addr, register int size, register char *data));
static void db_write_text __P((char *dst, int ch));
diff -r da98c358cb9f -r b5bba86b8841 sys/arch/amiga/amiga/locore.s
--- a/sys/arch/amiga/amiga/locore.s Mon Sep 06 21:50:39 1999 +0000
+++ b/sys/arch/amiga/amiga/locore.s Mon Sep 06 21:50:47 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.109 1999/04/29 16:22:03 christos Exp $ */
+/* $NetBSD: locore.s,v 1.110 1999/09/06 21:50:47 is Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -954,7 +954,7 @@
/* flush TLB and turn on caches */
- jbsr _TBIA | invalidate TLB
+ jbsr __TBIA | invalidate TLB
movl #CACHE_ON,d0
tstl d5
jeq Lcacheon
@@ -1392,7 +1392,7 @@
movl _CMAP2,a0
movl _CADDR2,sp@- | destination kernel VA
movl d0,a0@ | load in page table
- jbsr _TBIS | invalidate any old mapping
+ jbsr __TBIS | invalidate any old mapping
addql #4,sp
movl _CADDR2,a1 | destination addr
movl sp@(4),a0 | source addr
@@ -1409,7 +1409,6 @@
/*
* Invalidate entire TLB.
*/
-ENTRY(TBIA)
__TBIA:
cmpl #MMU_68040,_mmutype
jeq Ltbia040
@@ -1435,7 +1434,7 @@
/*
* Invalidate any TLB entry for given VA (TB Invalidate Single)
*/
-ENTRY(TBIS)
+__TBIS:
#ifdef DEBUG
tstl fulltflush | being conservative?
jne __TBIA | yes, flush entire TLB
@@ -1469,178 +1468,6 @@
#endif
rts
-/*
- * Invalidate supervisor side of TLB
- */
-ENTRY(TBIAS)
-#ifdef DEBUG
- tstl fulltflush | being conservative?
- jne __TBIA | yes, flush everything
-#endif
- cmpl #MMU_68040,_mmutype
- jeq Ltbias040
- tstl _mmutype
- jpl Lmc68851c | 68851?
- pflush #4,#4 | flush supervisor TLB entries
- movl #DC_CLEAR,d0
- movc d0,cacr | invalidate on-chip d-cache
- rts
-Lmc68851c:
- pflushs #4,#4 | flush supervisor TLB entries
- rts
-Ltbias040:
-| 68040 cannot specify supervisor/user on pflusha, so we flush all
- .word 0xf518 | pflusha
-#ifdef M68060
- cmpl #CPU_68060,_cputype
- jne Ltbiasno60
- movc cacr,d0
- orl #IC60_CABC,d0 | and clear all btc entries
- movc d0,cacr
-Ltbiasno60:
-#endif
- rts
-
-/*
- * Invalidate user side of TLB
- */
-ENTRY(TBIAU)
-#ifdef DEBUG
- tstl fulltflush | being conservative?
- jne __TBIA | yes, flush everything
-#endif
- cmpl #MMU_68040,_mmutype
- jeq Ltbiau040
- tstl _mmutype
- jpl Lmc68851d | 68851?
- pflush #0,#4 | flush user TLB entries
- movl #DC_CLEAR,d0
- movc d0,cacr | invalidate on-chip d-cache
- rts
-Lmc68851d:
- pflushs #0,#4 | flush user TLB entries
- rts
-Ltbiau040:
-| 68040 cannot specify supervisor/user on pflusha, so we flush all
- .word 0xf518 | pflusha
-#ifdef M68060
- cmpl #CPU_68060,_cputype
- jne Ltbiauno60
- movc cacr,d0
- orl #IC60_CUBC,d0 | but only user btc entries
- movc d0,cacr
-Ltbiauno60:
-#endif
- rts
-
-/*
- * Invalidate instruction cache
- */
-ENTRY(ICIA)
-ENTRY(ICPA)
-#if defined(M68030) || defined(M68020)
-#if defined(M68040) || defined(M68060)
- cmpl #MMU_68040,_mmutype
- jeq Licia040
-#endif
- movl #IC_CLEAR,d0
- movc d0,cacr | invalidate i-cache
- rts
-Licia040:
-#endif
-#if defined(M68040) || defined(M68060)
- .word 0xf498 | cinva ic, clears btc on 060
- rts
-#endif
-
-/*
- * Invalidate data cache.
- * NOTE: we do not flush 68030 on-chip cache as there are no aliasing
- * problems with DC_WA. The only cases we have to worry about are context
- * switch and TLB changes, both of which are handled "in-line" in resume
- * and TBI*.
- */
-ENTRY(DCIA)
-__DCIA:
- cmpl #MMU_68040,_mmutype
- jne Ldciax
- .word 0xf478 | cpusha dc
-Ldciax:
- rts
-
-ENTRY(DCIS)
-__DCIS:
- cmpl #MMU_68040,_mmutype
- jne Ldcisx
- .word 0xf478 | cpusha dc
- nop
-Ldcisx:
- rts
-
-ENTRY(DCIU)
-__DCIU:
- cmpl #MMU_68040,_mmutype
- jne Ldciux
- .word 0xf478 | cpusha dc
-Ldciux:
- rts
-
-| Invalid single cache line
-ENTRY(DCIAS)
-__DCIAS:
- cmpl #MMU_68040,_mmutype
- jne Ldciasx
- movl sp@(4),a0
- .word 0xf468 | cpushl dc,a0@
-Ldciasx:
- rts
-#if defined(M68040) || defined(M68060)
-ENTRY(ICPL) /* invalidate instruction physical cache line */
- movl sp@(4),a0 | address
- .word 0xf488 | cinvl ic,a0@
- rts
-ENTRY(ICPP) /* invalidate instruction physical cache page */
- movl sp@(4),a0 | address
- .word 0xf490 | cinvp ic,a0@
- rts
-ENTRY(DCPL) /* invalidate data physical cache line */
- movl sp@(4),a0 | address
- .word 0xf448 | cinvl dc,a0@
- rts
-ENTRY(DCPP) /* invalidate data physical cache page */
- movl sp@(4),a0 | address
- .word 0xf450 | cinvp dc,a0@
- rts
-ENTRY(DCPA) /* invalidate data physical all */
- .word 0xf458 | cinva dc
- rts
-ENTRY(DCFL) /* data cache flush line */
- movl sp@(4),a0 | address
- .word 0xf468 | cpushl dc,a0@
- rts
-ENTRY(DCFP) /* data cache flush page */
- movl sp@(4),a0 | address
- .word 0xf470 | cpushp dc,a0@
- rts
-#endif /* M68040 */
-
-ENTRY(PCIA)
-#if defined(M68030) || defined(M68030)
-#if defined(M68040) || defined(M68060)
- cmpl #MMU_68040,_mmutype
- jeq Lpcia040
-#endif
- movl #DC_CLEAR,d0
- movc d0,cacr | invalidate on-chip d-cache
- rts
-#endif
-#if defined(M68040) || defined(M68060)
-ENTRY(DCFA)
-Lpcia040:
- .word 0xf478 | cpusha dc
- rts
-#endif
-
ENTRY(ecacheon)
rts
diff -r da98c358cb9f -r b5bba86b8841 sys/arch/amiga/amiga/pmap.c
--- a/sys/arch/amiga/amiga/pmap.c Mon Sep 06 21:50:39 1999 +0000
+++ b/sys/arch/amiga/amiga/pmap.c Mon Sep 06 21:50:47 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.70 1999/08/03 21:50:18 is Exp $ */
+/* $NetBSD: pmap.c,v 1.71 1999/09/06 21:50:47 is Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -125,6 +125,9 @@
#include <machine/pte.h>
#include <machine/cpu.h>
#include <machine/vmparam.h>
+
+#include <m68k/cacheops.h>
+
#include <amiga/amiga/memlist.h>
/*
* Allocate various and sundry SYSMAPs used in the days of old VM
diff -r da98c358cb9f -r b5bba86b8841 sys/arch/amiga/amiga/sys_machdep.c
--- a/sys/arch/amiga/amiga/sys_machdep.c Mon Sep 06 21:50:39 1999 +0000
+++ b/sys/arch/amiga/amiga/sys_machdep.c Mon Sep 06 21:50:47 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sys_machdep.c,v 1.24 1999/07/08 23:44:57 thorpej Exp $ */
+/* $NetBSD: sys_machdep.c,v 1.25 1999/09/06 21:50:48 is Exp $ */
/*
* Copyright (c) 1982, 1986 Regents of the University of California.
@@ -51,6 +51,9 @@
#include <vm/vm.h>
+#include <machine/cpu.h>
+#include <m68k/cacheops.h>
+
#ifdef TRACE
int nvualarm;
@@ -108,8 +111,6 @@
}
#endif
-#include <machine/cpu.h>
-
/* XXX should be in an include file somewhere */
#define CC_PURGE 1
#define CC_FLUSH 2
diff -r da98c358cb9f -r b5bba86b8841 sys/arch/amiga/amiga/trap.c
--- a/sys/arch/amiga/amiga/trap.c Mon Sep 06 21:50:39 1999 +0000
+++ b/sys/arch/amiga/amiga/trap.c Mon Sep 06 21:50:47 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.69 1999/03/24 05:50:53 mrg Exp $ */
+/* $NetBSD: trap.c,v 1.70 1999/09/06 21:50:48 is Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -76,6 +76,7 @@
#include <machine/pte.h>
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