[src/trunk]: src/sys/arch/next68k/dev discovered the purpose of another bit i...

[dbj <dbj%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5507ffff76a9
branches:  trunk
changeset: 475866:5507ffff76a9
user:      dbj <dbj%NetBSD.org@localhost>
date:      Sat Aug 28 09:19:04 1999 +0000

description:
discovered the purpose of another bit in the dma control register.
DMACSR_READ is now a CSR status bit which can be used to know if current transfer is
from cpu to device.
the old DMACSR_READ bit is renamed DMACSR_SETREAD.  This is a control bit that tells
the dma transfer to be from cpu to device.

diffstat:

 sys/arch/next68k/dev/esp.c        |   4 ++--
 sys/arch/next68k/dev/mb8795.c     |   6 +++---
 sys/arch/next68k/dev/nextdma.c    |  10 +++++-----
 sys/arch/next68k/dev/nextdmareg.h |   7 ++++---
 sys/arch/next68k/dev/nextdmavar.h |   4 ++--
 5 files changed, 16 insertions(+), 15 deletions(-)

diffs (127 lines):

diff -r 8b6f1ff3d27b -r 5507ffff76a9 sys/arch/next68k/dev/esp.c
--- a/sys/arch/next68k/dev/esp.c        Sat Aug 28 09:18:08 1999 +0000
+++ b/sys/arch/next68k/dev/esp.c        Sat Aug 28 09:19:04 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: esp.c,v 1.24 1999/03/23 08:42:39 dbj Exp $     */
+/*     $NetBSD: esp.c,v 1.25 1999/08/28 09:19:04 dbj Exp $     */
 
 /*-
  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -960,7 +960,7 @@
        }
 
        nextdma_start(&esc->sc_scsi_dma, 
-                       (esc->sc_datain ? DMACSR_READ : DMACSR_WRITE));
+                       (esc->sc_datain ? DMACSR_SETREAD : DMACSR_SETWRITE));
 
        if (esc->sc_datain) { 
                NCR_WRITE_REG(sc, ESP_DCTL,
diff -r 8b6f1ff3d27b -r 5507ffff76a9 sys/arch/next68k/dev/mb8795.c
--- a/sys/arch/next68k/dev/mb8795.c     Sat Aug 28 09:18:08 1999 +0000
+++ b/sys/arch/next68k/dev/mb8795.c     Sat Aug 28 09:19:04 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mb8795.c,v 1.15 1999/08/05 01:51:00 dbj Exp $  */
+/*     $NetBSD: mb8795.c,v 1.16 1999/08/28 09:19:05 dbj Exp $  */
 /*
  * Copyright (c) 1998 Darrin B. Jewell
  * All rights reserved.
@@ -555,7 +555,7 @@
        nextdma_init(sc->sc_tx_nd);
        nextdma_init(sc->sc_rx_nd);
 
-       nextdma_start(sc->sc_rx_nd, DMACSR_READ);
+       nextdma_start(sc->sc_rx_nd, DMACSR_SETREAD);
 
        if (ifp->if_snd.ifq_head != NULL) {
                mb8795_start(ifp);
@@ -823,7 +823,7 @@
   bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap, 0,
                        sc->sc_tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 
-       nextdma_start(sc->sc_tx_nd, DMACSR_WRITE);
+       nextdma_start(sc->sc_tx_nd, DMACSR_SETWRITE);
 
 #if NBPFILTER > 0
   /*
diff -r 8b6f1ff3d27b -r 5507ffff76a9 sys/arch/next68k/dev/nextdma.c
--- a/sys/arch/next68k/dev/nextdma.c    Sat Aug 28 09:18:08 1999 +0000
+++ b/sys/arch/next68k/dev/nextdma.c    Sat Aug 28 09:19:04 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: nextdma.c,v 1.18 1999/08/17 05:09:13 dbj Exp $ */
+/*     $NetBSD: nextdma.c,v 1.19 1999/08/28 09:19:05 dbj Exp $ */
 /*
  * Copyright (c) 1998 Darrin B. Jewell
  * All rights reserved.
@@ -646,7 +646,7 @@
 void
 nextdma_start(nd, dmadir)
        struct nextdma_config *nd;
-       u_long dmadir;                                                          /*      DMACSR_READ or DMACSR_WRITE */
+       u_long dmadir;                                                          /*      DMACSR_SETREAD or DMACSR_SETWRITE */
 {
 
 #ifdef DIAGNOSTIC
@@ -671,8 +671,8 @@
 #endif
 
 #ifdef DIAGNOSTIC
-       if ((dmadir != DMACSR_READ) && (dmadir != DMACSR_WRITE)) {
-               panic("DMA: nextdma_start(), dmadir arg must be DMACSR_READ or DMACSR_WRITE\n");
+       if ((dmadir != DMACSR_SETREAD) && (dmadir != DMACSR_SETWRITE)) {
+               panic("DMA: nextdma_start(), dmadir arg must be DMACSR_SETREAD or DMACSR_SETWRITE\n");
        }
 #endif
 
@@ -690,7 +690,7 @@
        next_dma_rotate(nd);
 
        DPRINTF(("DMA initiating DMA %s of %d segments on intr(0x%b)\n",
-                       (nd->_nd_dmadir == DMACSR_READ ? "read" : "write"), nd->_nd_map->dm_nsegs,
+                       (nd->_nd_dmadir == DMACSR_SETREAD ? "read" : "write"), nd->_nd_map->dm_nsegs,
                        NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS));
 
        bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0);
diff -r 8b6f1ff3d27b -r 5507ffff76a9 sys/arch/next68k/dev/nextdmareg.h
--- a/sys/arch/next68k/dev/nextdmareg.h Sat Aug 28 09:18:08 1999 +0000
+++ b/sys/arch/next68k/dev/nextdmareg.h Sat Aug 28 09:19:04 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: nextdmareg.h,v 1.4 1999/03/14 10:31:05 dbj Exp $       */
+/*     $NetBSD: nextdmareg.h,v 1.5 1999/08/28 09:19:05 dbj Exp $       */
 /*
  * Copyright (c) 1998 Darrin B. Jewell
  * All rights reserved.
@@ -88,13 +88,14 @@
 /* read bits */
 #define        DMACSR_ENABLE           0x01000000      /* enable dma transfer */
 #define        DMACSR_SUPDATE          0x02000000      /* single update */
+#define        DMACSR_READ             0x04000000      /* dma is ina read operation */
 #define        DMACSR_COMPLETE         0x08000000      /* current dma has completed */
 #define        DMACSR_BUSEXC           0x10000000      /* bus exception occurred */
 /* write bits */
 #define        DMACSR_SETENABLE        0x00010000      /* set enable */
 #define        DMACSR_SETSUPDATE       0x00020000      /* set single update */
-#define        DMACSR_READ             0x00040000      /* dma from dev to mem */
-#define        DMACSR_WRITE            0x00000000      /* dma from mem to dev */
+#define        DMACSR_SETREAD          0x00040000      /* dma from dev to mem */
+#define        DMACSR_SETWRITE         0x00000000      /* dma from mem to dev */
 #define        DMACSR_CLRCOMPLETE      0x00080000      /* clear complete conditional */
 #define        DMACSR_RESET            0x00100000      /* clr cmplt, sup, enable */
 #define        DMACSR_INITBUF          0x00200000      /* initialize DMA buffers */
diff -r 8b6f1ff3d27b -r 5507ffff76a9 sys/arch/next68k/dev/nextdmavar.h
--- a/sys/arch/next68k/dev/nextdmavar.h Sat Aug 28 09:18:08 1999 +0000
+++ b/sys/arch/next68k/dev/nextdmavar.h Sat Aug 28 09:19:04 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: nextdmavar.h,v 1.7 1999/08/03 09:16:01 dbj Exp $       */
+/*     $NetBSD: nextdmavar.h,v 1.8 1999/08/28 09:19:06 dbj Exp $       */
 /*
  * Copyright (c) 1998 Darrin B. Jewell
  * All rights reserved.
@@ -53,7 +53,7 @@
        bus_dmamap_t _nd_map_cont;    /* map needed to continue DMA */
        int          _nd_idx_cont;              /* segment index to continue DMA */
 
-       int _nd_dmadir;                                                         /* DMACSR_READ or DMACSR_WRITE */
+       int _nd_dmadir;                                                         /* DMACSR_SETREAD or DMACSR_SETWRITE */
 };