[src/trunk]: src/sys/dev Make fwohci works on big endian cpu (e.g., powermac ...

[enami <enami%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/363ad7b924eb
branches:  trunk
changeset: 507170:363ad7b924eb
user:      enami <enami%NetBSD.org@localhost>
date:      Thu Mar 15 23:01:33 2001 +0000

description:
Make fwohci works on big endian cpu (e.g., powermac g4).

diffstat:

 sys/dev/ieee1394/fwohci.c    |  6 +++++-
 sys/dev/ieee1394/fwohcivar.h |  8 +++++---
 sys/dev/pci/fwohci_pci.c     |  8 +++++++-
 3 files changed, 17 insertions(+), 5 deletions(-)

diffs (63 lines):

diff -r e27a96d3b872 -r 363ad7b924eb sys/dev/ieee1394/fwohci.c
--- a/sys/dev/ieee1394/fwohci.c Thu Mar 15 22:49:27 2001 +0000
+++ b/sys/dev/ieee1394/fwohci.c Thu Mar 15 23:01:33 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fwohci.c,v 1.21 2001/03/14 06:46:17 onoe Exp $ */
+/*     $NetBSD: fwohci.c,v 1.22 2001/03/15 23:01:33 enami Exp $        */
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -528,6 +528,10 @@
 
        OHCI_CSR_WRITE(sc, OHCI_REG_HCControlClear,
            OHCI_HCControl_NoByteSwapData | OHCI_HCControl_APhyEnhanceEnable);
+#if BYTE_ORDER == BIG_ENDIAN
+       OHCI_CSR_WRITE(sc, OHCI_REG_HCControlSet,
+           OHCI_HCControl_NoByteSwapData);
+#endif
 
        OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskClear, ~0);
        OHCI_CSR_WRITE(sc, OHCI_REG_IntMaskSet, OHCI_Int_BusReset |
diff -r e27a96d3b872 -r 363ad7b924eb sys/dev/ieee1394/fwohcivar.h
--- a/sys/dev/ieee1394/fwohcivar.h      Thu Mar 15 22:49:27 2001 +0000
+++ b/sys/dev/ieee1394/fwohcivar.h      Thu Mar 15 23:01:33 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fwohcivar.h,v 1.7 2000/12/13 11:30:15 enami Exp $      */
+/*     $NetBSD: fwohcivar.h,v 1.8 2001/03/15 23:03:43 enami Exp $      */
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -161,7 +161,9 @@
 
 /* Macros to read and write the OHCI registers
  */
-#define        OHCI_CSR_WRITE(sc, reg, val)    bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, val)
-#define        OHCI_CSR_READ(sc, reg)  bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, reg)
+#define        OHCI_CSR_WRITE(sc, reg, val) \
+       bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, reg, htole32(val))
+#define        OHCI_CSR_READ(sc, reg) \
+       le32toh(bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, reg))
 
 #endif /* _DEV_IEEE1394_FWOHCIVAR_H_ */
diff -r e27a96d3b872 -r 363ad7b924eb sys/dev/pci/fwohci_pci.c
--- a/sys/dev/pci/fwohci_pci.c  Thu Mar 15 22:49:27 2001 +0000
+++ b/sys/dev/pci/fwohci_pci.c  Thu Mar 15 23:01:33 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fwohci_pci.c,v 1.7 2001/03/15 22:20:12 enami Exp $     */
+/*     $NetBSD: fwohci_pci.c,v 1.8 2001/03/15 23:01:34 enami Exp $     */
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -114,6 +114,12 @@
        pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
            csr | PCI_COMMAND_MASTER_ENABLE);
 
+#if BYTE_ORDER == BIG_ENDIAN
+       csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_OHCI_CONTROL_REGISTER);
+       pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_OHCI_CONTROL_REGISTER,
+           csr | PCI_GLOBAL_SWAP_BE);
+#endif
+
        /* Map and establish the interrupt. */
        if (pci_intr_map(pa, &ih)) {
                printf("%s: couldn't map interrupt\n", self->dv_xname);