[src/trunk]: src/sys/arch/i386/include Add some Model Specific Register defin...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b16a63f4e657
branches:  trunk
changeset: 484064:b16a63f4e657
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Fri Mar 24 19:06:07 2000 +0000

description:
Add some Model Specific Register definitions.  From FreeBSD.

diffstat:

 sys/arch/i386/include/specialreg.h |  58 +++++++++++++++++++++++++++++++++++++-
 1 files changed, 57 insertions(+), 1 deletions(-)

diffs (72 lines):

diff -r bf9ed3093bde -r b16a63f4e657 sys/arch/i386/include/specialreg.h
--- a/sys/arch/i386/include/specialreg.h        Fri Mar 24 18:16:33 2000 +0000
+++ b/sys/arch/i386/include/specialreg.h        Fri Mar 24 19:06:07 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.9 1999/12/13 01:31:30 sommerfeld Exp $        */
+/*     $NetBSD: specialreg.h,v 1.10 2000/03/24 19:06:07 thorpej Exp $  */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -120,6 +120,62 @@
 #define CPUID_FLAGS1   "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
 #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21FGPAT\22PSE36\23PN\24B19\25B20\26B21\27B22\30MMX\31FXSR\32XMM\33B26\34B27\35B28\36B29\37B30\40B31"
 
+/*
+ * Model-specific registers for the i386 family
+ */
+#define MSR_P5_MC_ADDR         0x000
+#define MSR_P5_MC_TYPE         0x001
+#define MSR_TSC                        0x010
+#define MSR_APICBASE           0x01b
+#define MSR_EBL_CR_POWERON     0x02a
+#define MSR_BIOS_UPDT_TRIG     0x079
+#define MSR_BIOS_SIGN          0x08b
+#define MSR_PERFCTR0           0x0c1
+#define MSR_PERFCTR1           0x0c2
+#define MSR_MTRRcap            0x0fe
+#define MSR_MCG_CAP            0x179
+#define MSR_MCG_STATUS         0x17a
+#define MSR_MCG_CTL            0x17b
+#define MSR_EVNTSEL0           0x186
+#define MSR_EVNTSEL1           0x187
+#define MSR_DEBUGCTLMSR                0x1d9
+#define MSR_LASTBRANCHFROMIP   0x1db
+#define MSR_LASTBRANCHTOIP     0x1dc
+#define MSR_LASTINTFROMIP      0x1dd
+#define MSR_LASTINTTOIP                0x1de
+#define MSR_ROB_CR_BKUPTMPDR6  0x1e0
+#define MSR_MTRRVarBase                0x200
+#define MSR_MTRR64kBase                0x250
+#define MSR_MTRR16kBase                0x258
+#define MSR_MTRR4kBase         0x268
+#define MSR_MTRRdefType                0x2ff
+#define MSR_MC0_CTL            0x400
+#define MSR_MC0_STATUS         0x401
+#define MSR_MC0_ADDR           0x402
+#define MSR_MC0_MISC           0x403
+#define MSR_MC1_CTL            0x404
+#define MSR_MC1_STATUS         0x405
+#define MSR_MC1_ADDR           0x406
+#define MSR_MC1_MISC           0x407
+#define MSR_MC2_CTL            0x408
+#define MSR_MC2_STATUS         0x409
+#define MSR_MC2_ADDR           0x40a
+#define MSR_MC2_MISC           0x40b
+#define MSR_MC4_CTL            0x40c
+#define MSR_MC4_STATUS         0x40d
+#define MSR_MC4_ADDR           0x40e
+#define MSR_MC4_MISC           0x40f
+#define MSR_MC3_CTL            0x410
+#define MSR_MC3_STATUS         0x411
+#define MSR_MC3_ADDR           0x412
+#define MSR_MC3_MISC           0x413
+
+/*
+ * Constants related to MTRRs
+ */
+#define MTRR_N64K              8       /* numbers of fixed-size entries */
+#define MTRR_N16K              16
+#define MTRR_N4K               64
 
 /*
  * the following four 3-byte registers control the non-cacheable regions.