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[src/trunk]: src/sys/arch/mvme68k/dev Flesh out the memory controller driver ...
details: https://anonhg.NetBSD.org/src/rev/091b3c9a1f78
branches: trunk
changeset: 513281:091b3c9a1f78
user: scw <scw%NetBSD.org@localhost>
date: Fri Jul 27 18:38:54 2001 +0000
description:
Flesh out the memory controller driver (at least for the MCECC chip)
and attach it at mainbus since it depends both PCCChip2 and VMEChip2
(or the VMEChip2 interrupter) starting first.
We can finally enable, detect and log DRAM ECC errors.
(The PROM disabled ECC checks by default)
diffstat:
sys/arch/mvme68k/dev/mainbus.c | 24 +-
sys/arch/mvme68k/dev/mainbus.h | 4 +-
sys/arch/mvme68k/dev/memc.c | 603 +++++++++++++++++++++++++++++++++++-
sys/arch/mvme68k/dev/memcreg.h | 61 +++-
sys/arch/mvme68k/dev/pcctwo.c | 6 +-
sys/arch/mvme68k/dev/pcctworeg.h | 4 +-
sys/arch/mvme68k/dev/vme_two_isr.c | 19 +-
sys/arch/mvme68k/dev/vme_twovar.h | 6 +-
8 files changed, 688 insertions(+), 39 deletions(-)
diffs (truncated from 951 to 300 lines):
diff -r 4587f0aeef8e -r 091b3c9a1f78 sys/arch/mvme68k/dev/mainbus.c
--- a/sys/arch/mvme68k/dev/mainbus.c Fri Jul 27 17:58:20 2001 +0000
+++ b/sys/arch/mvme68k/dev/mainbus.c Fri Jul 27 18:38:54 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.9 2001/07/06 19:00:13 scw Exp $ */
+/* $NetBSD: mainbus.c,v 1.10 2001/07/27 18:38:54 scw Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -204,6 +204,28 @@
#endif
/*
+ * Attach the memory controllers on mvme162->mvme177.
+ * Note: These *must* be attached after the PCCChip2/MCChip.
+ * They must also be attached *after* the VMEchip2 has been
+ * initialised (either by the driver, or the vmetwo_probe()
+ * call above).
+ */
+#if defined(MVME162) || defined(MVME172) || defined(MVME167) || defined(MVME177)
+#if defined(MVME147)
+ if (machineid != MVME_147)
+#endif
+ {
+ ma.ma_name = "memc";
+ ma.ma_dmat = &_mainbus_dma_tag;
+ ma.ma_bust = &_mainbus_space_tag;
+ ma.ma_offset = MAINBUS_MEMC1_OFFSET + intiobase_phys;
+ (void) config_found(self, &ma, mainbus_print);
+ ma.ma_offset = MAINBUS_MEMC2_OFFSET + intiobase_phys;
+ (void) config_found(self, &ma, mainbus_print);
+ }
+#endif
+
+ /*
* Attach Industry Pack modules on mvme162 and mvme172
*/
#if defined(MVME162) || defined(MVME172)
diff -r 4587f0aeef8e -r 091b3c9a1f78 sys/arch/mvme68k/dev/mainbus.h
--- a/sys/arch/mvme68k/dev/mainbus.h Fri Jul 27 17:58:20 2001 +0000
+++ b/sys/arch/mvme68k/dev/mainbus.h Fri Jul 27 18:38:54 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.h,v 1.4 2001/05/31 18:46:08 scw Exp $ */
+/* $NetBSD: mainbus.h,v 1.5 2001/07/27 18:38:54 scw Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -56,6 +56,8 @@
*/
#define MAINBUS_VMETWO_OFFSET 0x0000u
#define MAINBUS_PCCTWO_OFFSET 0x2000u
+#define MAINBUS_MEMC1_OFFSET 0x3000u
+#define MAINBUS_MEMC2_OFFSET 0x3100u
#define MAINBUS_IPACK_OFFSET 0x18000u /* mvme162/mvme172 only */
extern struct mvme68k_bus_space_tag _mainbus_space_tag;
diff -r 4587f0aeef8e -r 091b3c9a1f78 sys/arch/mvme68k/dev/memc.c
--- a/sys/arch/mvme68k/dev/memc.c Fri Jul 27 17:58:20 2001 +0000
+++ b/sys/arch/mvme68k/dev/memc.c Fri Jul 27 18:38:54 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: memc.c,v 1.3 2001/05/31 18:46:08 scw Exp $ */
+/* $NetBSD: memc.c,v 1.4 2001/07/27 18:38:55 scw Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -49,8 +49,15 @@
#include <machine/cpu.h>
#include <machine/bus.h>
+#include <mvme68k/dev/mainbus.h>
+#include <mvme68k/dev/memcreg.h>
#include <mvme68k/dev/pcctwovar.h>
-#include <mvme68k/dev/memcreg.h>
+#include <mvme68k/dev/pcctworeg.h>
+
+#include <dev/vme/vmevar.h>
+#include <mvme68k/dev/mvmebus.h>
+#include <mvme68k/dev/vme_twovar.h>
+#include <mvme68k/dev/vme_tworeg.h>
struct memc_softc {
struct device sc_dev;
@@ -68,8 +75,299 @@
extern struct cfdriver memc_cd;
-static void memc040_attach(struct memc_softc *, struct pcctwo_attach_args *);
-static void memecc_attach(struct memc_softc *, struct pcctwo_attach_args *);
+static void memc040_attach(struct memc_softc *);
+static void memecc_attach(struct memc_softc *);
+static void memc_hook_error_intr(struct memc_softc *, int (*)(void *));
+
+static int memecc_err_intr(void *);
+static void memecc_log_error(struct memc_softc *, u_int8_t, int, int);
+
+#define memc_reg_read(sc, off) \
+ bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (off))
+#define memc_reg_write(sc, off, v) \
+ bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (off), (v))
+
+/*
+ * Some tweakable parameters. Mind you, I don't recommend changing
+ * the irq level...
+ * XXX: This should probably be irq 7
+ */
+#define MEMC_IRQ_LEVEL 6
+#define MEMECC_SCRUBBER_PERIOD 14400 /* ~4 hours */
+
+/*
+ * The following stuff is used to decode the ECC syndrome code so
+ * that we can figure out exactly which address/bit needed to be
+ * corrected.
+ */
+#define MEMECC_SYN_BIT_MASK 0x0fu
+#define MEMECC_SYN_BANK_A 0x00u
+#define MEMECC_SYN_BANK_B 0x01u
+#define MEMECC_SYN_BANK_C 0x10u
+#define MEMECC_SYN_BANK_D 0x11u
+#define MEMECC_SYN_BANK_SHIFT 4
+#define MEMECC_SYN_BANK_MASK 0x03u
+#define MEMECC_SYN_CHECKBIT_ERR 0x80u
+#define MEMECC_SYN_INVALID 0xffu
+
+static u_int8_t memc_syn_decode[256] = {
+ MEMECC_SYN_INVALID, /* 0x00 */
+ MEMECC_SYN_CHECKBIT_ERR | 0, /* 0x01: Checkbit 0 */
+ MEMECC_SYN_CHECKBIT_ERR | 1, /* 0x02: Checkbit 1 */
+ MEMECC_SYN_INVALID, /* 0x03 */
+ MEMECC_SYN_CHECKBIT_ERR | 2, /* 0x04: Checkbit 2 */
+ MEMECC_SYN_INVALID, /* 0x05 */
+ MEMECC_SYN_INVALID, /* 0x06 */
+ MEMECC_SYN_BANK_C | 10, /* 0x07: Bank C 10/26 */
+ MEMECC_SYN_CHECKBIT_ERR | 3, /* 0x08: Checkbit 3 */
+ MEMECC_SYN_INVALID, /* 0x09 */
+ MEMECC_SYN_INVALID, /* 0x0a */
+ MEMECC_SYN_BANK_C | 13, /* 0x0b: Bank C 13/29 */
+ MEMECC_SYN_INVALID, /* 0x0c */
+ MEMECC_SYN_BANK_D | 1, /* 0x0d: Bank D 1/17 */
+ MEMECC_SYN_BANK_D | 2, /* 0x0e: Bank D 2/18 */
+ MEMECC_SYN_INVALID, /* 0x0f */
+ MEMECC_SYN_CHECKBIT_ERR | 4, /* 0x10: Checkbit 4 */
+ MEMECC_SYN_INVALID, /* 0x11 */
+ MEMECC_SYN_INVALID, /* 0x12 */
+ MEMECC_SYN_BANK_C | 14, /* 0x13: Bank C 14/30 */
+ MEMECC_SYN_INVALID, /* 0x14 */
+ MEMECC_SYN_BANK_D | 4, /* 0x15: Bank D 4/20 */
+ MEMECC_SYN_BANK_D | 5, /* 0x16: Bank D 5/21 */
+ MEMECC_SYN_INVALID, /* 0x17 */
+ MEMECC_SYN_INVALID, /* 0x18 */
+ MEMECC_SYN_BANK_D | 8, /* 0x19: Bank D 8/24 */
+ MEMECC_SYN_BANK_D | 9, /* 0x1a: Bank D 9/25 */
+ MEMECC_SYN_INVALID, /* 0x1b */
+ MEMECC_SYN_BANK_D | 10, /* 0x1c: Bank D 10/26 */
+ MEMECC_SYN_INVALID, /* 0x1d */
+ MEMECC_SYN_INVALID, /* 0x1e */
+ MEMECC_SYN_INVALID, /* 0x1f */
+ MEMECC_SYN_CHECKBIT_ERR | 5, /* 0x20: Checkbit 5 */
+ MEMECC_SYN_INVALID, /* 0x21 */
+ MEMECC_SYN_INVALID, /* 0x22 */
+ MEMECC_SYN_BANK_C | 0, /* 0x23: Bank C 0/16 */
+ MEMECC_SYN_INVALID, /* 0x24 */
+ MEMECC_SYN_BANK_D | 7, /* 0x25: Bank D 7/23 */
+ MEMECC_SYN_BANK_D | 6, /* 0x26: Bank D 6/22 */
+ MEMECC_SYN_INVALID, /* 0x27 */
+ MEMECC_SYN_INVALID, /* 0x28 */
+ MEMECC_SYN_BANK_A | 15, /* 0x29: Bank A 15/31 */
+ MEMECC_SYN_BANK_D | 12, /* 0x2a: Bank D 12/28 */
+ MEMECC_SYN_INVALID, /* 0x2b */
+ MEMECC_SYN_BANK_D | 13, /* 0x2c: Bank D 13/29 */
+ MEMECC_SYN_INVALID, /* 0x2d */
+ MEMECC_SYN_INVALID, /* 0x2e */
+ MEMECC_SYN_INVALID, /* 0x2f */
+ MEMECC_SYN_INVALID, /* 0x30 */
+ MEMECC_SYN_BANK_A | 14, /* 0x31: Bank A 14/30 */
+ MEMECC_SYN_BANK_A | 0, /* 0x32: Bank A 0/16 */
+ MEMECC_SYN_INVALID, /* 0x33 */
+ MEMECC_SYN_BANK_A | 1, /* 0x34: Bank A 1/17 */
+ MEMECC_SYN_INVALID, /* 0x35 */
+ MEMECC_SYN_INVALID, /* 0x36 */
+ MEMECC_SYN_INVALID, /* 0x37 */
+ MEMECC_SYN_BANK_A | 2, /* 0x38: Bank A 2/18 */
+ MEMECC_SYN_INVALID, /* 0x39 */
+ MEMECC_SYN_INVALID, /* 0x3a */
+ MEMECC_SYN_INVALID, /* 0x3b */
+ MEMECC_SYN_INVALID, /* 0x3c */
+ MEMECC_SYN_BANK_C | 3, /* 0x3d: Bank C 3/19 */
+ MEMECC_SYN_INVALID, /* 0x3e */
+ MEMECC_SYN_INVALID, /* 0x3f */
+ MEMECC_SYN_CHECKBIT_ERR | 6, /* 0x40: Checkbit 6 */
+ MEMECC_SYN_INVALID, /* 0x41 */
+ MEMECC_SYN_INVALID, /* 0x42 */
+ MEMECC_SYN_BANK_C | 1, /* 0x43: Bank C 1/17 */
+ MEMECC_SYN_INVALID, /* 0x44 */
+ MEMECC_SYN_BANK_C | 4, /* 0x45: Bank C 4/20 */
+ MEMECC_SYN_BANK_C | 8, /* 0x46: Bank C 8/24 */
+ MEMECC_SYN_INVALID, /* 0x47 */
+ MEMECC_SYN_INVALID, /* 0x48 */
+ MEMECC_SYN_BANK_C | 7, /* 0x49: Bank C 7/23 */
+ MEMECC_SYN_BANK_D | 15, /* 0x4a: Bank D 15/31 */
+ MEMECC_SYN_INVALID, /* 0x4b */
+ MEMECC_SYN_BANK_D | 14, /* 0x4c: Bank D 14/30 */
+ MEMECC_SYN_INVALID, /* 0x4d */
+ MEMECC_SYN_INVALID, /* 0x4e */
+ MEMECC_SYN_BANK_B | 3, /* 0x4f: Bank B 3/19 */
+ MEMECC_SYN_INVALID, /* 0x50 */
+ MEMECC_SYN_BANK_B | 4, /* 0x51: Bank B 4/20 */
+ MEMECC_SYN_BANK_B | 7, /* 0x52: Bank B 7/23 */
+ MEMECC_SYN_INVALID, /* 0x53 */
+ MEMECC_SYN_BANK_A | 4, /* 0x54: Bank A 4/20 */
+ MEMECC_SYN_INVALID, /* 0x55 */
+ MEMECC_SYN_INVALID, /* 0x56 */
+ MEMECC_SYN_INVALID, /* 0x57 */
+ MEMECC_SYN_BANK_A | 5, /* 0x58: Bank A 5/21 */
+ MEMECC_SYN_INVALID, /* 0x59 */
+ MEMECC_SYN_INVALID, /* 0x5a */
+ MEMECC_SYN_INVALID, /* 0x5b */
+ MEMECC_SYN_INVALID, /* 0x5c */
+ MEMECC_SYN_INVALID, /* 0x5d */
+ MEMECC_SYN_INVALID, /* 0x5e */
+ MEMECC_SYN_INVALID, /* 0x5f */
+ MEMECC_SYN_INVALID, /* 0x60 */
+ MEMECC_SYN_BANK_B | 5, /* 0x61: Bank B 5/21 */
+ MEMECC_SYN_BANK_B | 6, /* 0x62: Bank B 6/22 */
+ MEMECC_SYN_INVALID, /* 0x63 */
+ MEMECC_SYN_BANK_A | 8, /* 0x64: Bank A 8/24 */
+ MEMECC_SYN_INVALID, /* 0x65 */
+ MEMECC_SYN_INVALID, /* 0x66 */
+ MEMECC_SYN_INVALID, /* 0x67 */
+ MEMECC_SYN_BANK_A | 9, /* 0x68: Bank A 9/25 */
+ MEMECC_SYN_INVALID, /* 0x69 */
+ MEMECC_SYN_INVALID, /* 0x6a */
+ MEMECC_SYN_INVALID, /* 0x6b */
+ MEMECC_SYN_INVALID, /* 0x6c */
+ MEMECC_SYN_INVALID, /* 0x6d */
+ MEMECC_SYN_INVALID, /* 0x6e */
+ MEMECC_SYN_INVALID, /* 0x6f */
+ MEMECC_SYN_BANK_A | 10, /* 0x70: Bank A 10/26 */
+ MEMECC_SYN_INVALID, /* 0x71 */
+ MEMECC_SYN_INVALID, /* 0x72 */
+ MEMECC_SYN_INVALID, /* 0x73 */
+ MEMECC_SYN_INVALID, /* 0x74 */
+ MEMECC_SYN_INVALID, /* 0x75 */
+ MEMECC_SYN_INVALID, /* 0x76 */
+ MEMECC_SYN_INVALID, /* 0x77 */
+ MEMECC_SYN_INVALID, /* 0x78 */
+ MEMECC_SYN_INVALID, /* 0x79 */
+ MEMECC_SYN_BANK_C | 11, /* 0x7a: Bank C 11/27 */
+ MEMECC_SYN_INVALID, /* 0x7b */
+ MEMECC_SYN_INVALID, /* 0x7c */
+ MEMECC_SYN_INVALID, /* 0x7d */
+ MEMECC_SYN_INVALID, /* 0x7e */
+ MEMECC_SYN_INVALID, /* 0x7f */
+ MEMECC_SYN_CHECKBIT_ERR | 7, /* 0x80: Checkbit 7 */
+ MEMECC_SYN_INVALID, /* 0x81 */
+ MEMECC_SYN_INVALID, /* 0x82 */
+ MEMECC_SYN_BANK_C | 2, /* 0x83: Bank C 2/18 */
+ MEMECC_SYN_INVALID, /* 0x84 */
+ MEMECC_SYN_BANK_C | 5, /* 0x85: Bank C 5/21 */
+ MEMECC_SYN_BANK_C | 9, /* 0x86: Bank C 9/25 */
+ MEMECC_SYN_INVALID, /* 0x87 */
+ MEMECC_SYN_INVALID, /* 0x88 */
+ MEMECC_SYN_BANK_C | 6, /* 0x89: Bank C 6/22 */
+ MEMECC_SYN_BANK_C | 12, /* 0x8a: Bank C 12/28 */
+ MEMECC_SYN_INVALID, /* 0x8b */
+ MEMECC_SYN_BANK_D | 0, /* 0x8c: Bank D 0/16 */
+ MEMECC_SYN_INVALID, /* 0x8d */
+ MEMECC_SYN_INVALID, /* 0x8e */
+ MEMECC_SYN_INVALID, /* 0x8f */
+ MEMECC_SYN_INVALID, /* 0x90 */
+ MEMECC_SYN_BANK_B | 8, /* 0x91: Bank B 8/24 */
+ MEMECC_SYN_BANK_C | 15, /* 0x92: Bank C 15/31 */
+ MEMECC_SYN_INVALID, /* 0x93 */
+ MEMECC_SYN_BANK_A | 7, /* 0x94: Bank A 7/23 */
+ MEMECC_SYN_INVALID, /* 0x95 */
+ MEMECC_SYN_INVALID, /* 0x96 */
+ MEMECC_SYN_INVALID, /* 0x97 */
+ MEMECC_SYN_BANK_A | 6, /* 0x98: Bank A 6/22 */
+ MEMECC_SYN_INVALID, /* 0x99 */
+ MEMECC_SYN_INVALID, /* 0x9a */
+ MEMECC_SYN_INVALID, /* 0x9b */
+ MEMECC_SYN_INVALID, /* 0x9c */
+ MEMECC_SYN_INVALID, /* 0x9d */
+ MEMECC_SYN_BANK_B | 11, /* 0x9e: Bank B 11/27 */
+ MEMECC_SYN_INVALID, /* 0x9f */
+ MEMECC_SYN_INVALID, /* 0xa0 */
+ MEMECC_SYN_BANK_B | 9, /* 0xa1: Bank B 9/25 */
+ MEMECC_SYN_BANK_B | 12, /* 0xa2: Bank B 12/28 */
+ MEMECC_SYN_INVALID, /* 0xa3 */
+ MEMECC_SYN_BANK_B | 15, /* 0xa4: Bank B 15/31 */
+ MEMECC_SYN_INVALID, /* 0xa5 */
+ MEMECC_SYN_INVALID, /* 0xa6 */
+ MEMECC_SYN_BANK_A | 11, /* 0xa7: Bank A 11/27 */
+ MEMECC_SYN_BANK_A | 12, /* 0xa8: Bank A 12/28 */
+ MEMECC_SYN_INVALID, /* 0xa9 */
+ MEMECC_SYN_INVALID, /* 0xaa */
+ MEMECC_SYN_INVALID, /* 0xab */
+ MEMECC_SYN_INVALID, /* 0xac */
+ MEMECC_SYN_INVALID, /* 0xad */
+ MEMECC_SYN_INVALID, /* 0xae */
+ MEMECC_SYN_INVALID, /* 0xaf */
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