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[src/trunk]: src/sys/arch Update to reflect that unlike in m68k a.out environ...



details:   https://anonhg.NetBSD.org/src/rev/e677407d2520
branches:  trunk
changeset: 509756:e677407d2520
user:      kleink <kleink%NetBSD.org@localhost>
date:      Sat May 12 00:55:34 2001 +0000

description:
Update to reflect that unlike in m68k a.out environments, where the .align
directive is given a log2 argument, .align is given a linear argument in
m68k ELF environments.

diffstat:

 sys/arch/hp300/hp300/locore.s     |  10 +++++++++-
 sys/arch/mvme68k/mvme68k/locore.s |  10 +++++++++-
 sys/arch/news68k/news68k/locore.s |  10 +++++++++-
 sys/arch/sun3/sun3/locore.s       |  18 +++++++++++++++++-
 sys/arch/sun3/sun3x/locore.s      |  18 +++++++++++++++++-
 5 files changed, 61 insertions(+), 5 deletions(-)

diffs (213 lines):

diff -r 5faa4991b34a -r e677407d2520 sys/arch/hp300/hp300/locore.s
--- a/sys/arch/hp300/hp300/locore.s     Sat May 12 00:17:55 2001 +0000
+++ b/sys/arch/hp300/hp300/locore.s     Sat May 12 00:55:34 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.112 2000/11/26 11:47:24 jdolecek Exp $    */
+/*     $NetBSD: locore.s,v 1.113 2001/05/12 00:55:34 kleink Exp $      */
 
 /*
  * Copyright (c) 1994, 1995 Gordon W. Ross
@@ -1195,7 +1195,11 @@
 
 ASLOCAL(mdpflag)
        .byte   0               | copy of proc md_flags low byte
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 
 ASBSS(nullpcb,SIZEOF_PCB)
 
@@ -1860,7 +1864,11 @@
         * operations and that the loop will run from a single cache
         * half-line.
         */
+#ifdef __ELF__
        .align  8
+#else
+       .align  3
+#endif
 L_delay:
        subl    %d1,%d0
        jgt     L_delay
diff -r 5faa4991b34a -r e677407d2520 sys/arch/mvme68k/mvme68k/locore.s
--- a/sys/arch/mvme68k/mvme68k/locore.s Sat May 12 00:17:55 2001 +0000
+++ b/sys/arch/mvme68k/mvme68k/locore.s Sat May 12 00:55:34 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.76 2001/02/15 11:49:25 scw Exp $  */
+/*     $NetBSD: locore.s,v 1.77 2001/05/12 01:11:49 kleink Exp $       */
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -1265,7 +1265,11 @@
 
 ASLOCAL(mdpflag)
        .byte   0               | copy of proc md_flags low byte
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 
 ASBSS(nullpcb,SIZEOF_PCB)
 
@@ -1653,7 +1657,11 @@
         * operations and that the loop will run from a single cache
         * half-line.
         */
+#ifdef __ELF__
        .align  8
+#else
+       .align  3
+#endif
 L_delay:
        subl    %d1,%d0
        jgt     L_delay
diff -r 5faa4991b34a -r e677407d2520 sys/arch/news68k/news68k/locore.s
--- a/sys/arch/news68k/news68k/locore.s Sat May 12 00:17:55 2001 +0000
+++ b/sys/arch/news68k/news68k/locore.s Sat May 12 00:55:34 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.21 2001/04/21 11:54:25 tsutsui Exp $      */
+/*     $NetBSD: locore.s,v 1.22 2001/05/12 01:11:49 kleink Exp $       */
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -969,7 +969,11 @@
 
 ASLOCAL(mdpflag)
        .byte   0               | copy of proc md_flags low byte
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 
 ASBSS(nullpcb,SIZEOF_PCB)
 
@@ -1389,7 +1393,11 @@
         * operations and that the loop will run from a single cache
         * half-line.
         */
+#ifdef __ELF__
        .align  8
+#else
+       .align  3
+#endif
 L_delay:
        subl    %d1,%d0
        jgt     L_delay
diff -r 5faa4991b34a -r e677407d2520 sys/arch/sun3/sun3/locore.s
--- a/sys/arch/sun3/sun3/locore.s       Sat May 12 00:17:55 2001 +0000
+++ b/sys/arch/sun3/sun3/locore.s       Sat May 12 00:55:34 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.78 2001/02/22 07:11:12 chs Exp $  */
+/*     $NetBSD: locore.s,v 1.79 2001/05/12 01:11:50 kleink Exp $       */
 
 /*
  * Copyright (c) 1994, 1995 Gordon W. Ross
@@ -459,7 +459,11 @@
  * for which the CPU provides the vector=0x18+level.
  * These are installed in the interrupt vector table.
  */
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 GLOBAL(_isr_autovec)
        INTERRUPT_SAVEREG
        jbsr    _C_LABEL(isr_autovec)
@@ -467,7 +471,11 @@
        jra     _ASM_LABEL(rei)
 
 /* clock: see clock.c */
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 GLOBAL(_isr_clock)
        INTERRUPT_SAVEREG
        jbsr    _C_LABEL(clock_intr)
@@ -475,7 +483,11 @@
        jra     _ASM_LABEL(rei)
 
 | Handler for all vectored interrupts (i.e. VME interrupts)
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 GLOBAL(_isr_vectored)
        INTERRUPT_SAVEREG
        jbsr    _C_LABEL(isr_vectored)
@@ -973,7 +985,11 @@
         * operations and that the loop will run from a single cache
         * half-line.
         */
+#ifdef __ELF__
        .align  8
+#else
+       .align  3
+#endif
 L_delay:
        subl    %d1,%d0
        jgt     L_delay
diff -r 5faa4991b34a -r e677407d2520 sys/arch/sun3/sun3x/locore.s
--- a/sys/arch/sun3/sun3x/locore.s      Sat May 12 00:17:55 2001 +0000
+++ b/sys/arch/sun3/sun3x/locore.s      Sat May 12 00:55:34 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.45 2001/02/22 07:11:12 chs Exp $  */
+/*     $NetBSD: locore.s,v 1.46 2001/05/12 01:11:50 kleink Exp $       */
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -482,7 +482,11 @@
  * for which the CPU provides the vector=0x18+level.
  * These are installed in the interrupt vector table.
  */
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 GLOBAL(_isr_autovec)
        INTERRUPT_SAVEREG
        jbsr    _C_LABEL(isr_autovec)
@@ -490,7 +494,11 @@
        jra     _ASM_LABEL(rei)
 
 /* clock: see clock.c */
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 GLOBAL(_isr_clock)
        INTERRUPT_SAVEREG
        jbsr    _C_LABEL(clock_intr)
@@ -498,7 +506,11 @@
        jra     _ASM_LABEL(rei)
 
 | Handler for all vectored interrupts (i.e. VME interrupts)
+#ifdef __ELF__
+       .align  4
+#else
        .align  2
+#endif
 GLOBAL(_isr_vectored)
        INTERRUPT_SAVEREG
        jbsr    _C_LABEL(isr_vectored)
@@ -1108,7 +1120,11 @@
         * operations and that the loop will run from a single cache
         * half-line.
         */
+#ifdef __ELF__
        .align  8
+#else
+       .align  3
+#endif
 L_delay:
        subl    %d1,%d0
        jgt     L_delay



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