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[src/trunk]: src/sys o IEEE 754 floating-point completion code.
details: https://anonhg.NetBSD.org/src/rev/767db5cd188a
branches: trunk
changeset: 509083:767db5cd188a
user: ross <ross%NetBSD.org@localhost>
date: Thu Apr 26 03:10:44 2001 +0000
description:
o IEEE 754 floating-point completion code.
o Implement the architected FP_C "Floating Point Control Quadword"
diffstat:
sys/arch/alpha/alpha/db_instruction.h | 24 +-
sys/arch/alpha/alpha/fp_complete.c | 715 +++-
sys/arch/alpha/alpha/locore.s | 59 +-
sys/arch/alpha/alpha/machdep.c | 27 +-
sys/arch/alpha/alpha/sys_machdep.c | 32 +-
sys/arch/alpha/alpha/trap.c | 121 +-
sys/arch/alpha/alpha/vm_machdep.c | 7 +-
sys/arch/alpha/conf/files.alpha | 3 +-
sys/arch/alpha/include/alpha.h | 37 +-
sys/arch/alpha/include/cpu.h | 9 +-
sys/arch/alpha/include/fpu.h | 120 +
sys/arch/alpha/include/ieeefp.h | 58 +-
sys/arch/alpha/include/proc.h | 22 +-
sys/arch/alpha/include/sysarch.h | 3 +-
sys/arch/alpha/pci/cia.c | 8 +-
sys/compat/linux/arch/alpha/linux_machdep.c | 14 +-
sys/compat/osf1/osf1_misc.c | 41 +-
sys/lib/libkern/arch/alpha/Makefile.inc | 3 +-
sys/lib/libkern/milieu.h | 160 +
sys/lib/libkern/softfloat-macros.h | 745 +++
sys/lib/libkern/softfloat-specialize.h | 487 ++
sys/lib/libkern/softfloat.c | 5497 +++++++++++++++++++++++++++
sys/lib/libkern/softfloat.h | 370 +
23 files changed, 8398 insertions(+), 164 deletions(-)
diffs (truncated from 9054 to 300 lines):
diff -r 82168665316c -r 767db5cd188a sys/arch/alpha/alpha/db_instruction.h
--- a/sys/arch/alpha/alpha/db_instruction.h Thu Apr 26 02:53:46 2001 +0000
+++ b/sys/arch/alpha/alpha/db_instruction.h Thu Apr 26 03:10:44 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: db_instruction.h,v 1.6 2000/03/20 02:54:45 thorpej Exp $ */
+/* $NetBSD: db_instruction.h,v 1.7 2001/04/26 03:10:44 ross Exp $ */
/*
* Copyright (c) 1999 Christopher G. Demetriou. All rights reserved.
@@ -184,6 +184,16 @@
opcode : 6;
} float_format;
+ struct {
+ unsigned fc : 5,
+ opclass : 4,
+ src : 2,
+ rnd : 2,
+ trp : 3,
+ fb : 5,
+ fa : 5,
+ opcode : 6;
+ } float_detail;
/*
* PAL instructions just define the major opcode
@@ -221,7 +231,7 @@
#define op_logical 0x11 /* see LOGICAL sub-table */
#define op_bit 0x12 /* see BIT sub-table */
#define op_mul 0x13 /* see MUL sub-table */
- /* reserved */
+#define op_fix_float 0x14 /* if ALPHA_AMASK_FIX */
#define op_vax_float 0x15 /* see FLOAT sub-table */
#define op_ieee_float 0x16 /* see FLOAT sub-table */
#define op_any_float 0x17 /* see FLOAT sub-table */
@@ -411,6 +421,12 @@
* Load and store operations use opcodes op_ldf..op_stt
*/
+ /* src encoding from function, 9..10 */
+#define op_src_sf 0
+#define op_src_xd 1
+#define op_src_tg 2
+#define op_src_qq 3
+
/* any FLOAT, "function" opcodes (bits 5..11) */
#define op_cvtlq 0x010
@@ -427,7 +443,7 @@
#define op_fcmovgt 0x02f
#define op_cvtql 0x030
#define op_cvtql_v 0x130
-#define op_cvtql_sv 0x330
+#define op_cvtql_sv 0x530
/* ieee FLOAT, "function" opcodes (bits 5..11) */
@@ -520,6 +536,7 @@
#define op_mult_ud 0x1e2
#define op_divt_ud 0x1e3
#define op_cvtts_ud 0x1ec
+#define op_cvtst 0x2ac
#define op_adds_suc 0x500
#define op_subs_suc 0x501
#define op_muls_suc 0x502
@@ -562,6 +579,7 @@
#define op_mult_sud 0x5e2
#define op_divt_sud 0x5e3
#define op_cvtts_sud 0x5ec
+#define op_cvtst_u 0x6ac
#define op_adds_suic 0x700
#define op_subs_suic 0x701
#define op_muls_suic 0x702
diff -r 82168665316c -r 767db5cd188a sys/arch/alpha/alpha/fp_complete.c
--- a/sys/arch/alpha/alpha/fp_complete.c Thu Apr 26 02:53:46 2001 +0000
+++ b/sys/arch/alpha/alpha/fp_complete.c Thu Apr 26 03:10:44 2001 +0000
@@ -1,1 +1,714 @@
-/* $NetBSD: fp_complete.c,v 1.1 2001/04/22 20:47:22 ross Exp $ */
+/* $NetBSD: fp_complete.c,v 1.2 2001/04/26 03:10:44 ross Exp $ */
+
+/*-
+ * Copyright (c) 2001 Ross Harvey
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
+
+__KERNEL_RCSID(0, "$NetBSD: fp_complete.c,v 1.2 2001/04/26 03:10:44 ross Exp $");
+
+#include "opt_compat_osf1.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+
+#ifdef COMPAT_OSF1
+#include <compat/osf1/osf1_exec.h>
+#endif
+
+#include <machine/cpu.h>
+#include <machine/fpu.h>
+#include <machine/reg.h>
+#include <machine/alpha.h>
+#include <alpha/alpha/db_instruction.h>
+
+#include <lib/libkern/softfloat.h>
+
+#define TSWINSIZE 4 /* size of trap shadow window in u_int32_t units */
+
+/* Set Name Opcodes AARM C.* Symbols */
+
+#define CPUREG_CLASS (0xfUL << 0x10) /* INT[ALSM] */
+#define FPUREG_CLASS (0xfUL << 0x14) /* ITFP, FLT[ILV] */
+#define CHECKFUNCTIONCODE (1UL << 0x18) /* MISC */
+#define TRAPSHADOWBOUNDARY (1UL << 0x00 | /* PAL */\
+ 1UL << 0x19 | /* \PAL\ */\
+ 1UL << 0x1a | /* JSR */\
+ 1UL << 0x1b | /* \PAL\ */\
+ 1UL << 0x1d | /* \PAL\ */\
+ 1UL << 0x1e | /* \PAL\ */\
+ 1UL << 0x1f | /* \PAL\ */\
+ 0xffffUL << 0x30 | /* branch ops */\
+ CHECKFUNCTIONCODE)
+
+#define MAKE_FLOATXX(width, expwidth, sign, exp, msb, rest_of_frac) \
+ (u_int ## width ## _t)(sign) << ((width) - 1) |\
+ (u_int ## width ## _t)(exp) << ((width) - 1 - (expwidth)) |\
+ (u_int ## width ## _t)(msb) << ((width) - 1 - (expwidth) - 1) |\
+ (u_int ## width ## _t)(rest_of_frac)
+
+#define FLOAT32QNAN MAKE_FLOATXX(32, 8, 0, 0xff, 1, 0)
+#define FLOAT64QNAN MAKE_FLOATXX(64, 11, 0, 0x7ff, 1, 0)
+
+#define IS_SUBNORMAL(v) ((v)->exp == 0 && (v)->frac != 0)
+
+#define PREFILTER_SUBNORMAL(p,v) if ((p)->p_md.md_flags & IEEE_MAP_DMZ \
+ && IS_SUBNORMAL(v)) \
+ (v)->frac = 0; else
+
+#define POSTFILTER_SUBNORMAL(p,v) if ((p)->p_md.md_flags & IEEE_MAP_UMZ \
+ && IS_SUBNORMAL(v)) \
+ (v)->frac = 0; else
+
+ /* Alpha returns 2.0 for true, all zeroes for false. */
+
+#define CMP_RESULT(flag) ((flag) ? 4UL << 60 : 0L)
+
+ /* Move bits from sw fp_c to hw fpcr. */
+
+#define CRBLIT(sw, hw, m, offs) (((sw) & ~(m)) | ((hw) >> (offs) & (m)))
+
+/*
+ * Temporary trap shadow instrumentation. The [un]resolved counters
+ * could be kept permanently, as they provide information on whether
+ * user code has met AARM trap shadow generation requirements.
+ */
+
+struct alpha_shadow {
+ u_int64_t resolved; /* cases trigger pc found */
+ u_int64_t unresolved; /* cases it wasn't, code problems? */
+ u_int64_t scans; /* trap shadow scans */
+ u_int64_t len; /* number of instructions examined */
+ u_int64_t uop; /* bit mask of unexpected opcodes */
+ u_int64_t sqrts; /* ev6+ square root single count */
+ u_int64_t sqrtt; /* ev6+ square root double count */
+ u_int32_t ufunc; /* bit mask of unexpected functions */
+ u_int32_t max; /* max trap shadow scan */
+ u_int32_t nilswop; /* unexpected op codes */
+ u_int32_t nilswfunc; /* unexpected function codes */
+ u_int32_t nilanyop; /* this "cannot happen" */
+ u_int32_t vax; /* sigs from vax fp opcodes */
+} alpha_shadow, alpha_shadow_zero;
+
+static float64 float64_unk(float64, float64);
+static float64 compare_un(float64, float64);
+static float64 compare_eq(float64, float64);
+static float64 compare_lt(float64, float64);
+static float64 compare_le(float64, float64);
+static void cvt_qs_ts_st_gf_qf(u_int32_t, struct proc *);
+static void cvt_gd(u_int32_t, struct proc *);
+static void cvt_qt_dg_qg(u_int32_t, struct proc *);
+static void cvt_tq_gq(u_int32_t, struct proc *);
+
+static float32 (*swfp_s[])(float32, float32) = {
+ float32_add, float32_sub, float32_mul, float32_div,
+};
+
+static float64 (*swfp_t[])(float64, float64) = {
+ float64_add, float64_sub, float64_mul, float64_div,
+ compare_un, compare_eq, compare_lt, compare_le,
+ float64_unk, float64_unk, float64_unk, float64_unk
+};
+
+static void (*swfp_cvt[])(u_int32_t, struct proc *) = {
+ cvt_qs_ts_st_gf_qf, cvt_gd, cvt_qt_dg_qg, cvt_tq_gq
+};
+
+static void
+this_cannot_happen(int what_cannot_happen, int64_t bits)
+{
+ static int total;
+ alpha_instruction inst;
+ static u_int64_t reported;
+
+ inst.bits = bits;
+ ++alpha_shadow.nilswfunc;
+ if (bits != -1)
+ alpha_shadow.uop |= 1UL << inst.generic_format.opcode;
+ if (1UL << what_cannot_happen & reported)
+ return;
+ reported |= 1UL << what_cannot_happen;
+ if (total >= 1000)
+ return; /* right now, this return "cannot happen" */
+ ++total;
+ if (bits)
+ printf("FP instruction %x\n", (unsigned int)bits);
+ printf("FP event %d/%lx/%lx\n", what_cannot_happen, reported,
+ alpha_shadow.uop);
+ printf("Please report this to port-alpha-maintainer%netbsd.org@localhost\n");
+}
+
+static __inline void
+sts(unsigned int rn, s_float *v, struct proc *p)
+{
+ alpha_sts(rn, v);
+ PREFILTER_SUBNORMAL(p, v);
+}
+
+static __inline void
+stt(unsigned int rn, t_float *v, struct proc *p)
+{
+ alpha_stt(rn, v);
+ PREFILTER_SUBNORMAL(p, v);
+}
+
+static __inline void
+lds(unsigned int rn, s_float *v, struct proc *p)
+{
+ POSTFILTER_SUBNORMAL(p, v);
+ alpha_lds(rn, v);
+}
+
+static __inline void
+ldt(unsigned int rn, t_float *v, struct proc *p)
+{
+ POSTFILTER_SUBNORMAL(p, v);
+ alpha_ldt(rn, v);
+}
+
+static float64
+compare_lt(float64 a, float64 b)
+{
+ return CMP_RESULT(float64_lt(a, b));
+}
+
+static float64
+compare_le(float64 a, float64 b)
+{
+ return CMP_RESULT(float64_le(a, b));
+}
+
+static float64
+compare_un(float64 a, float64 b)
+{
+ if (float64_is_nan(a) | float64_is_nan(b)) {
+ if (float64_is_signaling_nan(a) | float64_is_signaling_nan(b))
+ float_set_invalid();
+ return CMP_RESULT(1);
+ }
+ return CMP_RESULT(0);
+}
+
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