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[src/trunk]: src/sys/arch/walnut Update for walnut.h/ibm405gp.h changes.
details: https://anonhg.NetBSD.org/src/rev/be71d7ea6524
branches: trunk
changeset: 511656:be71d7ea6524
user: simonb <simonb%NetBSD.org@localhost>
date: Sun Jun 24 01:15:41 2001 +0000
description:
Update for walnut.h/ibm405gp.h changes.
diffstat:
sys/arch/walnut/dev/ibm405gp.c | 67 +++++++++++++++++++-------------------
sys/arch/walnut/pci/pci_machdep.c | 22 +++++------
sys/arch/walnut/walnut/consinit.c | 4 +-
sys/arch/walnut/walnut/locore.S | 4 +-
sys/arch/walnut/walnut/mainbus.c | 12 +++---
5 files changed, 52 insertions(+), 57 deletions(-)
diffs (270 lines):
diff -r 8491e384dd35 -r be71d7ea6524 sys/arch/walnut/dev/ibm405gp.c
--- a/sys/arch/walnut/dev/ibm405gp.c Sun Jun 24 01:13:11 2001 +0000
+++ b/sys/arch/walnut/dev/ibm405gp.c Sun Jun 24 01:15:41 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ibm405gp.c,v 1.2 2001/06/22 11:37:49 simonb Exp $ */
+/* $NetBSD: ibm405gp.c,v 1.3 2001/06/24 01:15:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -40,7 +40,6 @@
#include <sys/systm.h>
#include <machine/bus.h>
-#include <machine/walnut.h>
#include <dev/pci/pcivar.h>
#include <powerpc/ibm4xx/ibm405gp.h>
@@ -54,7 +53,7 @@
{
if (pcicfg_ioh)
return;
- if (bus_space_map(pcicfg_iot, PCIL_BASE, 0x40 , 0, &pcicfg_ioh))
+ if (bus_space_map(pcicfg_iot, PCIL0_BASE, 0x40 , 0, &pcicfg_ioh))
panic("Cannot map PCI configuration registers\n");
}
@@ -69,29 +68,29 @@
setup_pcicfg_window();
/* Disable all three memory mappers */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0MA, 0x00000000); /* disabled */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM1MA, 0x00000000); /* disabled */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM2MA, 0x00000000); /* disabled */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM1MS, 0x00000000); /* Can't really disable PTM1. */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM2MS, 0x00000000); /* disabled */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0MA, 0x00000000); /* disabled */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1MA, 0x00000000); /* disabled */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2MA, 0x00000000); /* disabled */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1MS, 0x00000000); /* Can't really disable PTM1. */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM2MS, 0x00000000); /* disabled */
/* Setup memory map #0 */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0MA, 0xF0000001); /* 256M non-prefetchable, enabled */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0LA, PCI0_MEM_BASE);
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0PCILA, PCI0_MEM_BASE);
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PMM0PCIHA, 0);
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0LA, PCI0_MEM_BASE);
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCILA, PCI0_MEM_BASE);
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCIHA, 0);
/* Configure PCI bridge */
tag = pci_make_tag(0, 0, 0, 0);
// x = pci_conf_read(0, tag, PCI0_CMD); /* Read PCI command register */
// pci_conf_write(0, tag, PCI0_CMD, x | MA | ME); /* enable bus mastering and memory space */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM1MS, 0xF0000001); /* Enable PTM1 */
- bus_space_write_4(pcicfg_iot, pcicfg_ioh, PTM1LA, 0);
- pci_conf_write(0, tag, PCI0_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */
- pci_conf_write(0, tag, PCI0_PTM2BAR, 0);
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1MS, 0xF0000001); /* Enable PTM1 */
+ bus_space_write_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1LA, 0);
+ pci_conf_write(0, tag, PCIC0_PTM1BAR, 0); /* Set up proper PCI->Local address base. Always enabled */
+ pci_conf_write(0, tag, PCIC0_PTM2BAR, 0);
}
void galaxy_show_pci_map(void)
@@ -102,38 +101,38 @@
setup_pcicfg_window();
printf("Local -> PCI map\n");
- la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0LA);
- lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0MA);
- pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0PCILA);
- ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM0PCIHA);
+ la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0LA);
+ lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0MA);
+ pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCILA);
+ ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM0PCIHA);
printf("0: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
(lm & 2) ? "":"not ",
(lm & 1) ? "enabled":"disabled");
- la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1LA);
- lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1MA);
- pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1PCILA);
- ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM1PCIHA);
+ la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1LA);
+ lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1MA);
+ pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1PCILA);
+ ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM1PCIHA);
printf("1: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
(lm & 2) ? "":"not ",
(lm & 1) ? "enabled":"disabled");
- la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2LA);
- lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2MA);
- pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2PCILA);
- ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PMM2PCIHA);
+ la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2LA);
+ lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2MA);
+ pl = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2PCILA);
+ ph = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PMM2PCIHA);
printf("2: %08lx,%08lx -> %08lx%08lx %sprefetchable, %s\n", la, lm, ph, pl,
(lm & 2) ? "":"not ",
(lm & 1) ? "enabled":"disabled");
printf("PCI -> Local map\n");
tag = pci_make_tag(0, 0, 0, 0);
- pl = pci_conf_read(0, tag, PCI0_PTM1BAR);
- la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM1LA);
- lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM1MS);
+ pl = pci_conf_read(0, tag, PCIC0_PTM1BAR);
+ la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1LA);
+ lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM1MS);
printf("1: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
(lm & 1)?"enabled":"disabled");
- pl = pci_conf_read(0, tag, PCI0_PTM2BAR);
- la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM2LA);
- lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PTM2MS);
+ pl = pci_conf_read(0, tag, PCIC0_PTM2BAR);
+ la = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM2LA);
+ lm = bus_space_read_4(pcicfg_iot, pcicfg_ioh, PCIL0_PTM2MS);
printf("2: %08lx -> %08lx,%08lx %s\n", pl, la, lm,
(lm & 1)?"enabled":"disabled");
}
diff -r 8491e384dd35 -r be71d7ea6524 sys/arch/walnut/pci/pci_machdep.c
--- a/sys/arch/walnut/pci/pci_machdep.c Sun Jun 24 01:13:11 2001 +0000
+++ b/sys/arch/walnut/pci/pci_machdep.c Sun Jun 24 01:15:41 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.c,v 1.1 2001/06/13 06:02:00 simonb Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -70,14 +70,12 @@
static bus_space_tag_t pci_iot;
static bus_space_handle_t pci_ioh;
-#define OFF(r) ((r)-PCI0_CFGADDR)
-
void pci_machdep_init(void)
{
if (pci_ioh == 0) {
pci_iot = 0;
- if (bus_space_map(pci_iot,PCI0_CFGADDR,8,0,&pci_ioh)){
+ if (bus_space_map(pci_iot, PCIC0_BASE, 8, 0, &pci_ioh)){
panic("Cannot map PCI registers\n");
}
}
@@ -141,9 +139,9 @@
pcireg_t data;
/* 405GT BIOS disables interrupts here. Should we? --Art */
- bus_space_write_4(pci_iot,pci_ioh, OFF(PCI0_CFGADDR), tag | reg);
- data = bus_space_read_4(pci_iot,pci_ioh,OFF(PCI0_CFGDATA));
- bus_space_write_4(pci_iot,pci_ioh,OFF(PCI0_CFGADDR), 0); /* 405GP pass2 errata #6 */
+ bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, tag | reg);
+ data = bus_space_read_4(pci_iot, pci_ioh, PCIC0_CFGDATA);
+ bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, 0); /* 405GP pass2 errata #6 */
return data;
}
@@ -151,9 +149,9 @@
pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
{
- bus_space_write_4(pci_iot,pci_ioh, OFF(PCI0_CFGADDR), tag | reg);
- bus_space_write_4(pci_iot,pci_ioh,OFF(PCI0_CFGDATA), data);
- bus_space_write_4(pci_iot,pci_ioh,OFF(PCI0_CFGADDR), 0); /* 405GP pass2 errata #6 */
+ bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, tag | reg);
+ bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGDATA, data);
+ bus_space_write_4(pci_iot, pci_ioh, PCIC0_CFGADDR, 0); /* 405GP pass2 errata #6 */
}
@@ -179,7 +177,7 @@
case 3: *ihp = 2; break; /* Slot 1 Ext IRQ 5 */
case 4: *ihp = 1; break; /* Slot 0 Ext IRQ 6 */
default:
- printf("Hmm.. PCI device %d should not exist on this board\n",dev);
+ printf("Hmm.. PCI device %d should not exist on this board\n", dev);
goto bad;
}
return 0;
@@ -192,7 +190,7 @@
const char *
pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
{
- static char irqstr[8]; /* 4 + 2 + NULL + sanity */
+ static char irqstr[8]; /* 4 + 2 + NUL + sanity */
if (ih == 0 || ih >= ICU_LEN)
panic("pci_intr_string: bogus handle 0x%x\n", ih);
diff -r 8491e384dd35 -r be71d7ea6524 sys/arch/walnut/walnut/consinit.c
--- a/sys/arch/walnut/walnut/consinit.c Sun Jun 24 01:13:11 2001 +0000
+++ b/sys/arch/walnut/walnut/consinit.c Sun Jun 24 01:15:41 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: consinit.c,v 1.1 2001/06/13 06:02:01 simonb Exp $ */
+/* $NetBSD: consinit.c,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
/*
* Copyright (c) 1998
@@ -31,7 +31,7 @@
#include <sys/device.h>
#include <machine/bus.h>
-#include <machine/walnut.h>
+#include <powerpc/ibm4xx/ibm405gp.h>
#include "com.h"
#if (NCOM > 0)
diff -r 8491e384dd35 -r be71d7ea6524 sys/arch/walnut/walnut/locore.S
--- a/sys/arch/walnut/walnut/locore.S Sun Jun 24 01:13:11 2001 +0000
+++ b/sys/arch/walnut/walnut/locore.S Sun Jun 24 01:15:41 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.1 2001/06/13 06:02:01 simonb Exp $ */
+/* $NetBSD: locore.S,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
/*
@@ -83,10 +83,8 @@
#include <machine/psl.h>
#include <machine/trap.h>
#include <machine/asm.h>
-#include <machine/walnut.h>
#include <powerpc/spr.h>
-
#include <powerpc/ibm4xx/dcr.h>
#include <powerpc/ibm4xx/pmap.h>
diff -r 8491e384dd35 -r be71d7ea6524 sys/arch/walnut/walnut/mainbus.c
--- a/sys/arch/walnut/walnut/mainbus.c Sun Jun 24 01:13:11 2001 +0000
+++ b/sys/arch/walnut/walnut/mainbus.c Sun Jun 24 01:15:41 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.3 2001/06/22 13:21:35 simonb Exp $ */
+/* $NetBSD: mainbus.c,v 1.4 2001/06/24 01:15:41 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -79,12 +79,12 @@
#include <machine/bus.h>
#include <machine/walnut.h>
+#include <powerpc/ibm4xx/ibm405gp.h>
+
#include <dev/pci/pcivar.h>
#include <dev/pci/pcidevs.h>
#include <dev/pci/pciconf.h>
-#include <powerpc/ibm4xx/ibm405gp.h>
-
/*
* The devices built in to the 405GP cpu.
*/
@@ -96,9 +96,9 @@
{ "com", UART0_BASE, 5 },
{ "com", UART1_BASE, 6 },
{ "dsrtc", NVRAM_BASE, -1 },
- { "emac", MIO6_START, 9 }, /* XXX: really irq 9..15 */
- { "gpio", MIO5_START, -1 },
- { "i2c", MIO4_START, -1 },
+ { "emac", EMAC0_BASE, 9 }, /* XXX: really irq 9..15 */
+ { "gpio", GPIO0_BASE, -1 },
+ { "i2c", IIC0_BASE, -1 },
{ "wdog", -1, -1 },
{ "pckbc", KEY_MOUSE_BASE, -1 }, /* XXX: really irq x..x+1 */
{ NULL }
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