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[src/trunk]: src/sys/arch files.ixp12x0
details: https://anonhg.NetBSD.org/src/rev/9918b4848b8b
branches: trunk
changeset: 543119:9918b4848b8b
user: ichiro <ichiro%NetBSD.org@localhost>
date: Mon Feb 17 20:51:52 2003 +0000
description:
files.ixp12x0
no need device ixpcom in evbarm/conf/files.evbarm move it to
arm/ixp12x0/files.ixp12x0
ixp12x0_com.c:
some fix around address handling
1. Do not call bus_space_map() in ixpcominit(). Calling bus_space_map()
is not safe here, because bus_space_map() calls uvm_km_valloc() but
uvm is not yet initialized.
2. Use dv_unit to determine console instead comparering iobase.
Now you can attach ixpcom0 with physical address like this:
ixpcom* at ixpsip? addr 0x90000000 size 0x4000
Statically mapped address (0xf0000000) is still usable.
ixp12x0_clk:
1. access PLL_CFG register via bus_space
2. Make the delay() working correctly. (bug fix)
3. Start the timer device without interrupt on attach time.
Now delay() called before cpu_initclocks() works fine.
ixp12x0_pci:
1.Mapping PCI type0/1 configuration space to the upper address.
2."PCI I/O Cycle Access" mapping to same virtual address(VA==PA)
but size of this mapping increase to 1MByte because fails
cause couldnt set L2 table.
3.use bus_space address handling in ixp12x0_pci.c.
diffstat:
sys/arch/arm/ixp12x0/files.ixp12x0 | 6 +-
sys/arch/arm/ixp12x0/ixp12x0.c | 69 ++++++++++-----
sys/arch/arm/ixp12x0/ixp12x0_clk.c | 97 +++++++++++----------
sys/arch/arm/ixp12x0/ixp12x0_clkreg.h | 7 +-
sys/arch/arm/ixp12x0/ixp12x0_com.c | 129 ++++++++++-------------------
sys/arch/arm/ixp12x0/ixp12x0_comreg.h | 3 +-
sys/arch/arm/ixp12x0/ixp12x0_intr.c | 9 +-
sys/arch/arm/ixp12x0/ixp12x0_io.c | 21 +---
sys/arch/arm/ixp12x0/ixp12x0_pci.c | 119 +++++++++++++++++++-------
sys/arch/arm/ixp12x0/ixp12x0_pci_dma.c | 22 +++-
sys/arch/arm/ixp12x0/ixp12x0_pcireg.h | 11 ++-
sys/arch/arm/ixp12x0/ixp12x0reg.h | 63 ++++++++------
sys/arch/arm/ixp12x0/ixp12x0var.h | 17 ++-
sys/arch/evbarm/conf/files.evbarm | 7 +-
sys/arch/evbarm/ixm1200/ixm1200_pci.c | 31 ++++---
sys/arch/evbarm/ixm1200/ixp12x0_mainbus.c | 4 +-
sys/arch/evbarm/ixm1200/nappi_nppb.c | 18 +--
sys/arch/evbarm/ixm1200/nappi_nr.c | 5 +-
18 files changed, 351 insertions(+), 287 deletions(-)
diffs (truncated from 1334 to 300 lines):
diff -r 8a73f1fbf973 -r 9918b4848b8b sys/arch/arm/ixp12x0/files.ixp12x0
--- a/sys/arch/arm/ixp12x0/files.ixp12x0 Mon Feb 17 20:32:04 2003 +0000
+++ b/sys/arch/arm/ixp12x0/files.ixp12x0 Mon Feb 17 20:51:52 2003 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.ixp12x0,v 1.3 2003/01/03 01:08:00 thorpej Exp $
+# $NetBSD: files.ixp12x0,v 1.4 2003/02/17 20:51:52 ichiro Exp $
#
# Configuration info for Intel IXP12x0 CPU support
#
@@ -23,3 +23,7 @@
device ixpclk
attach ixpclk at ixpsip
file arch/arm/ixp12x0/ixp12x0_clk.c ixpclk needs-flag
+
+# IXM1200 serial device
+device ixpcom: tty
+file arch/arm/ixp12x0/ixp12x0_com.c ixpcom needs-flag
diff -r 8a73f1fbf973 -r 9918b4848b8b sys/arch/arm/ixp12x0/ixp12x0.c
--- a/sys/arch/arm/ixp12x0/ixp12x0.c Mon Feb 17 20:32:04 2003 +0000
+++ b/sys/arch/arm/ixp12x0/ixp12x0.c Mon Feb 17 20:51:52 2003 +0000
@@ -1,6 +1,6 @@
-/* $NetBSD: ixp12x0.c,v 1.5 2003/01/01 00:46:15 thorpej Exp $ */
+/* $NetBSD: ixp12x0.c,v 1.6 2003/02/17 20:51:52 ichiro Exp $ */
/*
- * Copyright (c) 2002
+ * Copyright (c) 2002, 2003
* Ichiro FUKUHARA <ichiro%ichiro.org@localhost>.
* All rights reserved.
*
@@ -60,13 +60,29 @@
/*
* Subregion for PCI Configuration Spase Registers
*/
- if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0,
- IXP12X0_PCI_SIZE, &sc->sc_pci_ioh))
- panic("%s: unable to subregion PCI registers",
- sc->sc_dev.dv_xname);
+ if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+ IXP12X0_PCI_VBASE - IXP12X0_IO_VBASE,
+ IXP12X0_PCI_SIZE, &sc->sc_pci_ioh))
+ panic("%s: unable to subregion PCI registers",
+ sc->sc_dev.dv_xname);
+
+ if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+ IXP12X0_PCI_TYPE0_VBASE - IXP12X0_IO_VBASE,
+ IXP12X0_PCI_TYPE0_SIZE, &sc->sc_conf0_ioh))
+ panic("%s: unable to subregion PCI Configutation 0\n",
+ sc->sc_dev.dv_xname);
+
+ if (bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+ IXP12X0_PCI_TYPE1_VBASE - IXP12X0_IO_VBASE,
+ IXP12X0_PCI_TYPE1_SIZE, &sc->sc_conf1_ioh))
+ panic("%s: unable to subregion PCI Configutation 1\n",
+ sc->sc_dev.dv_xname);
/*
* PCI bus reset
*/
+ /* disable PCI command */
+ bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
+ PCI_COMMAND_STATUS_REG, 0xffff0000);
/* XXX assert PCI reset Mode */
reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
SA_CONTROL) &~ SA_CONTROL_PNR;
@@ -84,8 +100,10 @@
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
DBELL_SA_MASK, 0x0);
+ /* We setup a 1:1 memory map of bus<->physical addresses */
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
- PCI_ADDR_EXT, 0);
+ PCI_ADDR_EXT,
+ PCI_ADDR_EXT_PMSA(IXP12X0_PCI_MEM_HWBASE));
/* XXX Negate PCI reset */
reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
@@ -96,31 +114,27 @@
/*
* specify window size of memory access and SDRAM.
*/
- reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
- IXP_PCI_MEM_BAR) | IXP1200_PCI_MEM_BAR;
- bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
- IXP_PCI_MEM_BAR, reg);
+ bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR,
+ IXP1200_PCI_MEM_BAR & IXP_PCI_MEM_BAR_MASK);
- reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
- IXP_PCI_IO_BAR) | IXP1200_PCI_IO_BAR;
- bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
- IXP_PCI_IO_BAR, reg);
+ bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR,
+ IXP1200_PCI_IO_BAR & IXP_PCI_IO_BAR_MASK);
- reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
- IXP_PCI_DRAM_BAR) | IXP1200_PCI_DRAM_BAR;
- bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
- IXP_PCI_DRAM_BAR, reg);
+ bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR,
+ IXP1200_PCI_DRAM_BAR & IXP_PCI_DRAM_BAR_MASK);
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
CSR_BASE_ADDR_MASK, CSR_BASE_ADDR_MASK_1M);
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
DRAM_BASE_ADDR_MASK, DRAM_BASE_ADDR_MASK_256MB);
-#if DEBUG
- printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\n",
+#ifdef PCI_DEBUG
+ printf("IXP_PCI_MEM_BAR = 0x%08x\nIXP_PCI_IO_BAR = 0x%08x\nIXP_PCI_DRAM_BAR = 0x%08x\nPCI_ADDR_EXT = 0x%08x\nCSR_BASE_ADDR_MASK = 0x%08x\nDRAM_BASE_ADDR_MASK = 0x%08x\n",
bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_MEM_BAR),
bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_IO_BAR),
bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, IXP_PCI_DRAM_BAR),
+ bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_ADDR_EXT),
+ bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, CSR_BASE_ADDR_MASK),
bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, DRAM_BASE_ADDR_MASK));
#endif
/* Initialize complete */
@@ -139,10 +153,11 @@
reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,
PCI_COMMAND_STATUS_REG) |
PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
+ PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE |
PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,
PCI_COMMAND_STATUS_REG, reg);
-#if DEBUG
+#ifdef PCI_DEBUG
printf("PCI_COMMAND_STATUS_REG = 0x%08x\n",
bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, PCI_COMMAND_STATUS_REG));
#endif
@@ -152,7 +167,11 @@
ixp12x0_io_bs_init(&sc->ia_pci_iot, sc);
ixp12x0_mem_bs_init(&sc->ia_pci_memt, sc);
ixp12x0_pci_init(&sc->ia_pci_chipset, sc);
- ixp12x0_pci_dma_init(&sc->ia_pci_dmat, sc);
+
+ /*
+ * Initialize the DMA tags.
+ */
+ ixp12x0_pci_dma_init(sc);
/*
* Attach the PCI bus.
@@ -213,13 +232,13 @@
{ "PCI Type0 Configuration Space",
IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
- IXP12X0_PCI_TYPEX_SIZE,
+ IXP12X0_PCI_TYPE0_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
{ "PCI Type1 Configuration Space",
IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
- IXP12X0_PCI_TYPEX_SIZE,
+ IXP12X0_PCI_TYPE1_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE, },
diff -r 8a73f1fbf973 -r 9918b4848b8b sys/arch/arm/ixp12x0/ixp12x0_clk.c
--- a/sys/arch/arm/ixp12x0/ixp12x0_clk.c Mon Feb 17 20:32:04 2003 +0000
+++ b/sys/arch/arm/ixp12x0/ixp12x0_clk.c Mon Feb 17 20:51:52 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ixp12x0_clk.c,v 1.5 2002/10/02 05:02:30 thorpej Exp $ */
+/* $NetBSD: ixp12x0_clk.c,v 1.6 2003/02/17 20:51:52 ichiro Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
@@ -69,6 +69,7 @@
bus_addr_t sc_baseaddr;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_pll_ioh;
u_int32_t sc_clock_count;
u_int32_t sc_count_per_usec;
@@ -132,7 +133,7 @@
struct cfdata *match;
void *aux;
{
- return (1);
+ return 2;
}
static void
@@ -141,8 +142,9 @@
struct device *self;
void *aux;
{
- struct ixpclk_softc *sc = (struct ixpclk_softc*) self;
- struct ixpsip_attach_args *sa = aux;
+ struct ixpclk_softc *sc = (struct ixpclk_softc*) self;
+ struct ixpsip_attach_args *sa = aux;
+ u_int32_t ccf;
printf("\n");
@@ -156,12 +158,33 @@
if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0,
&sc->sc_ioh))
panic("%s: Cannot map registers", self->dv_xname);
+ if (bus_space_map(sa->sa_iot, sa->sa_addr + IXPCLK_PLL_CFG_OFFSET,
+ IXPCLK_PLL_CFG_SIZE, 0, &sc->sc_pll_ioh))
+ panic("%s: Cannot map registers", self->dv_xname);
/* disable all channel and clear interrupt status */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CONTROL,
IXPCL_DISABLE | IXPCL_PERIODIC | IXPCL_STP_CORE);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CLEAR, 0);
- printf("%s: IXP12x0 Interval Timer\n", sc->sc_dev.dv_xname);
+
+
+ ccf = bus_space_read_4(sc->sc_iot, sc->sc_pll_ioh, 0)
+ & IXP12X0_PLL_CFG_CCF;
+ sc->sc_coreclock_freq = ccf_to_coreclock[ccf];
+
+ sc->sc_clock_count = sc->sc_coreclock_freq / hz;
+ sc->sc_count_per_usec = sc->sc_coreclock_freq / 1000000;
+
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CLEAR, IXPT_CLEAR);
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_LOAD,
+ sc->sc_clock_count);
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CONTROL,
+ IXPCL_ENABLE | IXPCL_PERIODIC | IXPCL_STP_CORE);
+
+ printf("%s: IXP12x0 Interval Timer (core clock %d.%03dMHz)\n",
+ sc->sc_dev.dv_xname,
+ sc->sc_coreclock_freq / 1000000,
+ (sc->sc_coreclock_freq % 1000000) / 1000);
}
/*
@@ -173,11 +196,6 @@
ixpclk_intr(void *arg)
{
- /* XXX XXX */
- if (!(IXPREG(IXPPCI_IRQ_RAW_STATUS)
- & (1U << (IXPPCI_INTR_T1 - SYS_NIRQ))))
- return (0);
-
bus_space_write_4(ixpclk_sc->sc_iot, ixpclk_sc->sc_ioh,
IXPCLK_CLEAR, 1);
@@ -212,27 +230,17 @@
cpu_initclocks()
{
struct ixpclk_softc* sc = ixpclk_sc;
- u_int32_t ccf;
stathz = profhz = 0;
printf("clock: hz = %d stathz = %d\n", hz, stathz);
- ccf = IXPREG(IXP12X0_PLL_CFG) & IXP12X0_PLL_CFG_CCF;
- sc->sc_coreclock_freq = ccf_to_coreclock[ccf];
-
- printf("pll_cfg:ccf = %x coreclock frequency = %dHz\n",
- ccf, sc->sc_coreclock_freq);
-
- sc->sc_clock_count = sc->sc_coreclock_freq / hz;
- sc->sc_count_per_usec = sc->sc_coreclock_freq / 10000000;
-
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CONTROL,
+ IXPCL_DISABLE);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CLEAR, IXPT_CLEAR);
ixp12x0_intr_establish(IXPPCI_INTR_T1, IPL_CLOCK, ixpclk_intr, NULL);
- IXPREG(IXPPCI_IRQ_ENABLE_SET) = (1U << (IXPPCI_INTR_T1 - SYS_NIRQ));
-
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_LOAD,
sc->sc_clock_count);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXPCLK_CONTROL,
@@ -311,27 +319,23 @@
* Delay for at least N microseconds.
*/
void
-delay(usecs)
- u_int usecs;
+delay(unsigned int usecs)
{
- u_int32_t tick, otick, delta;
- int j, csec, usec;
+ u_int32_t count;
+ u_int32_t tick;
+ u_int32_t otick;
+ u_int32_t delta;
+ int j;
+ int csec, usec;
- csec = usecs / 10000;
- usec = usecs % 10000;
-
if (ixpclk_sc == NULL) {
- static u_int32_t coreclock_freq = 0;
-
#ifdef DEBUG
- printf("delay: called befor initialize ixpclk\n");
+ printf("delay: called befor start ixpclk\n");
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