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[src/trunk]: src/sys/arch move some definitions of register block size from s...
details: https://anonhg.NetBSD.org/src/rev/0178bcac1c25
branches: trunk
changeset: 551005:0178bcac1c25
user: bsh <bsh%NetBSD.org@localhost>
date: Wed Aug 27 03:46:05 2003 +0000
description:
move some definitions of register block size from s3c24[10]0reg.h
to s3c24x0reg.h when they are same for S3C2410 and 2400, and rename them as
S3C24X0_FOO_SIZE.
diffstat:
sys/arch/arm/s3c2xx0/s3c2400reg.h | 11 +----------
sys/arch/arm/s3c2xx0/s3c2410.c | 12 ++++++------
sys/arch/arm/s3c2xx0/s3c2410reg.h | 15 +++------------
sys/arch/arm/s3c2xx0/s3c24x0reg.h | 24 +++++++++++++++++++-----
sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c | 6 +++---
5 files changed, 32 insertions(+), 36 deletions(-)
diffs (275 lines):
diff -r 1cc49e8c8ab3 -r 0178bcac1c25 sys/arch/arm/s3c2xx0/s3c2400reg.h
--- a/sys/arch/arm/s3c2xx0/s3c2400reg.h Wed Aug 27 03:35:35 2003 +0000
+++ b/sys/arch/arm/s3c2xx0/s3c2400reg.h Wed Aug 27 03:46:05 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: s3c2400reg.h,v 1.1 2003/07/31 19:49:41 bsh Exp $ */
+/* $NetBSD: s3c2400reg.h,v 1.2 2003/08/27 03:46:05 bsh Exp $ */
/*
* Copyright (c) 2002, 2003 Genetec corp. All rights reserved.
@@ -55,9 +55,7 @@
* Physical address of integrated peripherals
*/
#define S3C2400_MEMCTL_BASE 0x14000000 /* memory controller */
-#define S3C2400_MEMCTL_SIZE 0x34
#define S3C2400_USBHC_BASE 0x14200000 /* USB Host controller */
-#define S3C2400_USBHC_SIZE 0x5c
#define S3C2400_INTCTL_BASE 0x14400000 /* Interrupt controller */
#define S3C2400_INTCTL_SIZE 0x18
#define S3C2400_DMAC_BASE 0x14600000 /* DMA controllers */
@@ -65,20 +63,14 @@
#define S3C2400_CLKMAN_BASE 0x14800000 /* clock & power management */
#define S3C2400_CLKMAN_SIZE 0x18
#define S3C2400_LCDC_BASE 0x14a00000
-#define S3C2400_LCDC_SIZE 0x54
#define S3C2400_UART_BASE 0x15000000
#define S3C2400_UART_BASE(n) (S3C2400_UART_BASE+0x4000*(n))
-#define S3C2400_UART_SIZE 0x2c
#define S3C2400_TIMER_BASE 0x15100000 /* Timers */
-#define S3C2400_PWM_SIZE 0x44
#define S3C2400_USBDC_BASE 0x15200000 /* USB Device controller */
#define S3C2400_USBDC_SIZE 0x1fc
#define S3C2400_WDT_BASE 0x15300000 /* Watch dog timer */
-#define S3C2400_WDT_SIZE 0x0c
#define S3C2400_IIC_BASE 0x15400000
-#deifne S3C2400_IIC_SIZE 0x0c
#define S3C2400_IIS_BASE 0x15508000
-#deifne S3C2400_IIS_SIZE 0x14
#define S3C2400_GPIO_BASE 0x15600000
#define S3C2400_GPIO_SIZE 0x5c
#define S3C2400_RTC_BASE 0x15700040
@@ -86,7 +78,6 @@
#define S3C2400_ADC_BASE 0x15800000 /* A/D converter */
#define S3C2400_ADC_SIZE 0x08
#define S3C2400_SPI_BASE 0x15900000
-#define S3C2400_SPI_SIZE 0x18
#define S3C2400_MMC_BASE 0x15a00000
#define S3C2400_MMC_SIZE 0x40
diff -r 1cc49e8c8ab3 -r 0178bcac1c25 sys/arch/arm/s3c2xx0/s3c2410.c
--- a/sys/arch/arm/s3c2xx0/s3c2410.c Wed Aug 27 03:35:35 2003 +0000
+++ b/sys/arch/arm/s3c2xx0/s3c2410.c Wed Aug 27 03:46:05 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: s3c2410.c,v 1.3 2003/08/05 11:26:54 bsh Exp $ */
+/* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */
/*
* Copyright (c) 2003 Genetec corporation. All rights reserved.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: s3c2410.c,v 1.3 2003/08/05 11:26:54 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -132,22 +132,22 @@
/* Memory controller */
if (bus_space_map(iot, S3C2410_MEMCTL_BASE,
- S3C2410_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
+ S3C24X0_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
FAIL("MEMC");
/* Clock manager */
if (bus_space_map(iot, S3C2410_CLKMAN_BASE,
- S3C2410_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
+ S3C24X0_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
FAIL("CLK");
#if 0
/* Real time clock */
if (bus_space_map(iot, S3C2410_RTC_BASE,
- S3C2410_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
+ S3C24X0_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
FAIL("RTC");
#endif
if (bus_space_map(iot, S3C2410_TIMER_BASE,
- S3C2410_TIMER_SIZE, 0, &sc->sc_timer_ioh))
+ S3C24X0_TIMER_SIZE, 0, &sc->sc_timer_ioh))
FAIL("TIMER");
/* calculate current clock frequency */
diff -r 1cc49e8c8ab3 -r 0178bcac1c25 sys/arch/arm/s3c2xx0/s3c2410reg.h
--- a/sys/arch/arm/s3c2xx0/s3c2410reg.h Wed Aug 27 03:35:35 2003 +0000
+++ b/sys/arch/arm/s3c2xx0/s3c2410reg.h Wed Aug 27 03:46:05 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: s3c2410reg.h,v 1.2 2003/08/04 10:24:15 bsh Exp $ */
+/* $NetBSD: s3c2410reg.h,v 1.3 2003/08/27 03:46:05 bsh Exp $ */
/*
* Copyright (c) 2003 Genetec corporation. All rights reserved.
@@ -55,39 +55,28 @@
* Physical address of integrated peripherals
*/
#define S3C2410_MEMCTL_BASE 0x48000000 /* memory controller */
-#define S3C2410_MEMCTL_SIZE 0x34
#define S3C2410_USBHC_BASE 0x49000000 /* USB Host controller */
-#define S3C2410_USBHC_SIZE 0x5c
#define S3C2410_INTCTL_BASE 0x4a000000 /* Interrupt controller */
-#define S3C2410_INTCTL_SIZE 0x20
#define S3C2410_DMAC_BASE 0x4b000000
#define S3C2410_DMAC_SIZE 0xe4
#define S3C2410_CLKMAN_BASE 0x4c000000 /* clock & power management */
-#define S3C2410_CLKMAN_SIZE 0x18
#define S3C2410_LCDC_BASE 0x4d000000 /* LCD controller */
-#define S3C2410_LCDC_SIZE 0x64
#define S3C2410_NANDFC_BASE 0x4e000000 /* NAND Flash controller */
#define S3C2410_NANDFC_SIZE 0x18
#define S3C2410_UART0_BASE 0x50000000
#define S3C2410_UART_BASE(n) (S3C2410_UART0_BASE+0x4000*(n))
-#define S3C2410_UART_SIZE 0x2c
#define S3C2410_TIMER_BASE 0x51000000
-#define S3C2410_TIMER_SIZE 0x44
#define S3C2410_USBDC_BASE 0x5200140
#define S3C2410_USBDC_SIZE 0x130
#define S3C2410_WDT_BASE 0x53000000
-#define S3C2410_WDT_SIZE 0x0c
#define S3C2410_IIC_BASE 0x54000000
-#define S3C2410_IIC_SIZE 0x0c
#define S3C2410_IIS_BASE 0x55000000
-#define S3C2410_IIS_SIZE 0x14
#define S3C2410_GPIO_BASE 0x56000000
#define S3C2410_GPIO_SIZE 0xb4
#define S3C2410_ADC_BASE 0x58000000
#define S3C2410_ADC_SIZE 0x14
#define S3C2410_SPI0_BASE 0x59000000
#define S3C2410_SPI1_BASE 0x59000020
-#define S3C2410_SPI1_SIZE 0x18
#define S3C2410_SDI_BASE 0x5a000000 /* SD Interface */
#define S3C2410_SDI_SIZE 0x44
@@ -120,6 +109,8 @@
#define S3C2410_INT_TXD0 (S3C2410_SUBIRQ_MIN+1) /* UART0 Tx interrupt */
#define S3C2410_INT_RXD0 (S3C2410_SUBIRQ_MIN+0) /* UART0 Rx interrupt */
+#define S3C2410_INTCTL_SIZE 0x20
+
/* Clock control: CLKCON register */
#define CLKCON_SPI (1<<18)
diff -r 1cc49e8c8ab3 -r 0178bcac1c25 sys/arch/arm/s3c2xx0/s3c24x0reg.h
--- a/sys/arch/arm/s3c2xx0/s3c24x0reg.h Wed Aug 27 03:35:35 2003 +0000
+++ b/sys/arch/arm/s3c2xx0/s3c24x0reg.h Wed Aug 27 03:46:05 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: s3c24x0reg.h,v 1.2 2003/08/04 12:19:38 bsh Exp $ */
+/* $NetBSD: s3c24x0reg.h,v 1.3 2003/08/27 03:46:05 bsh Exp $ */
/*
* Copyright (c) 2003 Genetec corporation All rights reserved.
@@ -52,7 +52,7 @@
#define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */
#define MEMCTL_BANKCON0 0x04 /* Boot ROM control */
-#define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */)
+#define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */
#define BANKCON_MT_SHIFT 15
#define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT)
#define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT)
@@ -91,8 +91,10 @@
#define MEMCTL_MRSRB7 0x30
#define MRSR_CL_SHIFT 4 /* CAS Latency */
+#define S3C24X0_MEMCTL_SIZE 0x34
+
/* USB Host controller */
-/* XXX */
+#define S3C24X0_USBHC_SIZE 0x5c
/* Interrupt controller */
#define INTCTL_PRIORITY 0x0c /* IRQ Priority control */
@@ -128,12 +130,12 @@
#define S3C24X0_INT_TIMER2 12
#define S3C24X0_INT_TIMER1 11
#define S3C24X0_INT_TIMER0 10
-#define S3C24X0_INT_TIMER(n) (10+(n)) /* External interrupt [4:0] */
+#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */
#define S3C24X0_INT_WDT 9 /* Watch dog timer */
#define S3C24X0_INT_TICK 8
#define S3C2410_INT_BFLT 7 /* Battery fault */
#define S3C2410_INT_8_23 5 /* Ext int 8..23 */
-#define S3C2410_INT_4_7 4 /* Ext int 8..23 */
+#define S3C2410_INT_4_7 4 /* Ext int 4..7 */
#define S3C24X0_INT_EXT(n) (n) /* External interrupt [7:0] for 2400,
* [3:0] for 2410 */
/* DMA controller */
@@ -161,9 +163,11 @@
#define CLKDIVN_HDIVN (1<<1)
#define CLKDIVN_PDIVN (1<<0)
+#define S3C24X0_CLKMAN_SIZE 0x18
/* LCD controller */
/* XXX */
+#define S3C24X0_LCDC_SIZE 0x64
/* Timer */
#define TIMER_TCFG0 0x00 /* Timer configuration */
@@ -188,6 +192,8 @@
#define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer 0 */
#define TIMER_TO(n) (0x14+0x0c*(n)) /* count observation 0 */
+#define S3C24X0_TIMER_SIZE 0x44
+
/* UART */
/* diffs to s3c2800 */
#define UMCON_AFC (1<<4) /* auto flow control */
@@ -195,6 +201,8 @@
#define ULCON_IR (1<<6)
#define ULCON_PARITY_SHIFT 3
+#define S3C24X0_UART_SIZE 0x2c
+
/* USB device */
/* XXX */
@@ -216,15 +224,21 @@
#define WDT_WTDAT 0x04 /* timer data */
#define WDT_WTCNT 0x08 /* timer count */
+#define S3C24X0_WDT_SIZE 0x0c
+
/* IIC */ /* XXX */
+#define S3C24X0_IIC_SIZE 0x0c
+
/* IIS */ /* XXX */
+#define S3C24X0_IIS_SIZE 0x14
/* RTC */ /* XXX */
/* ADC */ /* XXX */
/* SPI */ /* XXX */
+#define S3C24X0_SPI_SIZE 0x18
diff -r 1cc49e8c8ab3 -r 0178bcac1c25 sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c
--- a/sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c Wed Aug 27 03:35:35 2003 +0000
+++ b/sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c Wed Aug 27 03:46:05 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: smdk2410_machdep.c,v 1.4 2003/08/05 11:32:35 bsh Exp $ */
+/* $NetBSD: smdk2410_machdep.c,v 1.5 2003/08/27 03:46:05 bsh Exp $ */
/*
* Copyright (c) 2002, 2003 Fujitsu Component Limited
@@ -105,7 +105,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: smdk2410_machdep.c,v 1.4 2003/08/05 11:32:35 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: smdk2410_machdep.c,v 1.5 2003/08/27 03:46:05 bsh Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -424,7 +424,7 @@
bootstrap_bs_map(&bootstrap_bs_tag, S3C2410_INTCTL_BASE,
S3C2410_INTCTL_SIZE, 0, &temp_softc.sc_sx.sc_intctl_ioh);
bootstrap_bs_map(&bootstrap_bs_tag, S3C2410_CLKMAN_BASE,
- S3C2410_CLKMAN_SIZE, 0, &temp_softc.sc_sx.sc_clkman_ioh);
+ S3C24X0_CLKMAN_SIZE, 0, &temp_softc.sc_sx.sc_clkman_ioh);
#undef __LED
#define __LED(x) \
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