[src/trunk]: src/sys/arch/mips/mips Fix the order of the CPU revision and com...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cdaed7f9afd3
branches:  trunk
changeset: 536139:cdaed7f9afd3
user:      simonb <simonb%NetBSD.org@localhost>
date:      Mon Sep 09 03:42:04 2002 +0000

description:
Fix the order of the CPU revision and company options fields in the cpu
table for the Alchemy CPUs; successfully recognises an Au1500 now.

diffstat:

 sys/arch/mips/mips/mips_machdep.c |  16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diffs (44 lines):

diff -r 32a4da899621 -r cdaed7f9afd3 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Mon Sep 09 03:01:26 2002 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Mon Sep 09 03:42:04 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mips_machdep.c,v 1.148 2002/09/06 13:18:43 gehenna Exp $       */
+/*     $NetBSD: mips_machdep.c,v 1.149 2002/09/09 03:42:04 simonb Exp $        */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -120,7 +120,7 @@
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.148 2002/09/06 13:18:43 gehenna Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.149 2002/09/09 03:42:04 simonb Exp $");
 
 #include "opt_cputype.h"
 #include "opt_compat_netbsd.h"
@@ -384,19 +384,19 @@
        { MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0,
          MIPS64_FLAGS,                         "20Kc"                  },
 
-       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1000, -1, -1, 0,
+       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1000 (Rev 1 core)"   },
-       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1000, -1, -1, 0,
+       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1000 (Rev 2 core)"   },
 
-       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1500, -1, -1, 0,
+       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1500 (Rev 1 core)"   },
-       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1500, -1, -1, 0,
+       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1500 (Rev 2 core)"   },
 
-       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1100, -1, -1, 0,
+       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1100 (Rev 1 core)"   },
-       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1100, -1, -1, 0,
+       { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0,
          MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1100 (Rev 2 core)"   },
 
        /* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */