[src/trunk]: src/sys/arch/hpcarm/sa11x0 add SA-1110 MCP(Multimedia communicat...

[ichiro <ichiro%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/23bcabd45e4b
branches:  trunk
changeset: 512625:23bcabd45e4b
user:      ichiro <ichiro%NetBSD.org@localhost>
date:      Wed Jul 11 16:02:25 2001 +0000

description:
add SA-1110 MCP(Multimedia communications Port) register definition

diffstat:

 sys/arch/hpcarm/sa11x0/sa11x0_mcpreg.h |  65 ++++++++++++++++++++++++++++++++++
 1 files changed, 65 insertions(+), 0 deletions(-)

diffs (69 lines):

diff -r 86858b98d904 -r 23bcabd45e4b sys/arch/hpcarm/sa11x0/sa11x0_mcpreg.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/hpcarm/sa11x0/sa11x0_mcpreg.h    Wed Jul 11 16:02:25 2001 +0000
@@ -0,0 +1,65 @@
+/*     $NetBSD: sa11x0_mcpreg.h,v 1.1 2001/07/11 16:02:25 ichiro Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA (ichiro%ichiro.org@localhost).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *     This product includes software developed by the NetBSD
+ *     Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* SA11[01]0 MCP(Multimedia communications Port) */
+
+#define SAMCP_NPORTS   7
+
+#define SAMCP_CR0      0x00    /* MCP control register 0 */
+/* MCP control register 1 locate PPC area */
+
+#define SAMCP_DR0      0x08    /* MCP data register 0 */
+#define SAMCP_DR1      0x0C    /* MCP data register 1 */
+#define SAMCP_DR2      0x10    /* MCP data register 2 */
+#define SAMCP_SR       0x18    /* MCP status register */
+
+/* MCP control register 0*/
+#define CR0_ASD
+#define CR0_TSD
+#define CR0_MCE                (1 << 16)       /* MCP enable */
+#define CR0_ECS                (1 << 17)       /* External clock used */ 
+#define CR0_ADM                (1 << 18)       /* A/D sampling mode */
+#define CR0_TTE                (1 << 19)       /* Telecom tx FIFO intr enable */
+#define CR0_TRE                (1 << 20)       /* Telecom rx FIFO intr enable */
+#define CR0_ATE                (1 << 21)       /* Audio tx FIFO intr enable */
+#define CR0_ARE                (1 << 22)       /* Audio rx FIFO intr enable */
+#define CR0_LBM                (1 << 23)       /* Output of serial shifter connect
+                                          to Input of serial shifter internal */
+#define CR0_ECP(x)     ((x) << 24)     /* External clock prescaler */
+
+/* MCP control register 0 */
+#define CR1_CFS                (1 << 20)