Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/sparc64/include clean-up, reformat __asm statements.
details: https://anonhg.NetBSD.org/src/rev/c275882bf6b1
branches: trunk
changeset: 567516:c275882bf6b1
user: petrov <petrov%NetBSD.org@localhost>
date: Thu Jun 17 19:35:14 2004 +0000
description:
clean-up, reformat __asm statements.
diffstat:
sys/arch/sparc64/include/ctlreg.h | 581 +++++++++++++++++++++++--------------
1 files changed, 364 insertions(+), 217 deletions(-)
diffs (truncated from 816 to 300 lines):
diff -r 6ca21298f1c1 -r c275882bf6b1 sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Thu Jun 17 18:30:54 2004 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Thu Jun 17 19:35:14 2004 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.32 2004/03/22 12:24:37 nakayama Exp $ */
+/* $NetBSD: ctlreg.h,v 1.33 2004/06/17 19:35:14 petrov Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -23,6 +23,9 @@
*
*/
+#ifndef _SPARC_CTLREG_H_
+#define _SPARC_CTLREG_H_
+
/*
* Sun 4u control registers. (includes address space definitions
* and some registers in control space).
@@ -185,7 +188,6 @@
* The following are 4u control registers
*/
-
/* Get the CPU's UPAID */
#define UPA_CR_MID(x) (((x)>>17)&0x1f)
#define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG))
@@ -265,17 +267,13 @@
#define SFSR_W 0x00004 /* DMMU: attempted write */
#define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */
#define SFSR_FV 0x00001 /* Fault is valid */
-#define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO|SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
+#define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \
+ SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
-#if 0
-/* Old bits */
-#define SFSR_BITS "\40\16VAT\15VAD\14NFO\13ASI\12A\11NF\10PRIV\7E\6NUCLEUS\5SECONDCTX\4PRIV\3W\2OW\1FV"
-#else
-/* New bits */
#define SFSR_BITS "\177\20" \
- "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" "b\11NF\0" "b\10PRIV\0" \
- "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" "b\3W\0" "b\2OW\0" "b\1FV\0"
-#endif
+ "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \
+ "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \
+ "b\3W\0" "b\2OW\0" "b\1FV\0"
/* ASFR bits */
#define ASFR_ME 0x100000000LL
@@ -455,36 +453,18 @@
* D$ so we need to flush the D$ to make sure we don't get data pollution.
*/
-static __inline__ u_char lduba __P((paddr_t loc, int asi));
-static __inline__ u_short lduha __P((paddr_t loc, int asi));
-static __inline__ u_int lda __P((paddr_t loc, int asi));
-static __inline__ int ldswa __P((paddr_t loc, int asi));
-static __inline__ u_int64_t ldxa __P((paddr_t loc, int asi));
-static __inline__ u_int64_t ldda __P((paddr_t loc, int asi));
-
-static __inline__ void stba __P((paddr_t loc, int asi, u_char value));
-static __inline__ void stha __P((paddr_t loc, int asi, u_short value));
-static __inline__ void sta __P((paddr_t loc, int asi, u_int value));
-static __inline__ void stxa __P((paddr_t loc, int asi, u_int64_t value));
-static __inline__ void stda __P((paddr_t loc, int asi, u_int64_t value));
-
-#if 0
-static __inline__ unsigned int casa __P((paddr_t loc, int asi,
- unsigned int value, unsigned int oldvalue));
-static __inline__ u_int64_t casxa __P((paddr_t loc, int asi,
- u_int64_t value, u_int64_t oldvalue));
-#endif
-
#ifdef __arch64__
static __inline__ u_char
lduba(paddr_t loc, int asi)
{
register unsigned int _lduba_v;
- __asm __volatile("wr %2,%%g0,%%asi; "
- " lduba [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
- "=r" (_lduba_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
+ __asm __volatile(
+ "wr %2,%%g0,%%asi; "
+ "lduba [%1]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi"
+ : "=r" (_lduba_v)
+ : "r" ((unsigned long)(loc)), "r" (asi));
return (_lduba_v);
}
#else
@@ -495,18 +475,28 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
-" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; "
-" membar #Sync; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" membar #Sync; wr %%g0, 0x82, %%asi" :
- "=&r" (_lduba_v), "=&r" (_pstate) :
- "r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi));
+ __asm __volatile(
+ "wr %4,%%g0,%%asi; "
+ "sllx %3,32,%0; "
+ "rdpr %%pstate,%1; "
+ "or %0,%2,%0; "
+ "wrpr %1,8,%%pstate; "
+ "membar #Sync; "
+ "lduba [%0]%%asi,%0; "
+ "wrpr %1,0,%%pstate; "
+ "membar #Sync; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lduba_v), "=&r" (_pstate)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
} else {
- __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; lduba [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduba_v) :
- "r" ((unsigned long)(loc)),
- "r" (_loc_hi), "r" (asi));
+ __asm __volatile(
+ "wr %3,%%g0,%%asi "
+ "sllx %2,32,%0; "
+ "or %0,%1,%0; "
+ "lduba [%0]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lduba_v)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
}
return (_lduba_v);
}
@@ -519,10 +509,12 @@
{
register unsigned int _lduha_v;
- __asm __volatile("wr %2,%%g0,%%asi; lduha [%1]%%asi,%0; "
- " wr %%g0, 0x82, %%asi" :
- "=r" (_lduha_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
+ __asm __volatile(
+ "wr %2,%%g0,%%asi; "
+ "lduha [%1]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi "
+ : "=r" (_lduha_v)
+ : "r" ((unsigned long)(loc)), "r" (asi));
return (_lduha_v);
}
#else
@@ -534,17 +526,28 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; "
-" rdpr %%pstate,%1; wrpr %1,8,%%pstate; "
-" or %0,%2,%0; membar #Sync; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" membar #Sync; wr %%g0, 0x82, %%asi" :
- "=&r" (_lduha_v), "=&r" (_pstate) :
- "r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi));
+ __asm __volatile(
+ "wr %4,%%g0,%%asi; "
+ "sllx %3,32,%0; "
+ "rdpr %%pstate,%1; "
+ "wrpr %1,8,%%pstate; "
+ "or %0,%2,%0; "
+ "membar #Sync; "
+ "lduha [%0]%%asi,%0; "
+ "wrpr %1,0,%%pstate; "
+ "membar #Sync; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lduha_v), "=&r" (_pstate)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
} else {
- __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; lduha [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lduha_v) :
- "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
+ __asm __volatile(
+ "wr %3,%%g0,%%asi; "
+ "sllx %2,32,%0; "
+ "or %0,%1,%0; "
+ "lduha [%0]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lduha_v)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
}
return (_lduha_v);
}
@@ -558,9 +561,11 @@
{
register unsigned int _lda_v;
- __asm __volatile("wr %2,%%g0,%%asi; lda [%1]%%asi,%0" :
- "=r" (_lda_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
+ __asm __volatile(
+ "wr %2,%%g0,%%asi; "
+ "lda [%1]%%asi,%0 "
+ : "=r" (_lda_v)
+ : "r" ((unsigned long)(loc)), "r" (asi));
return (_lda_v);
}
@@ -570,10 +575,12 @@
{
register int _lda_v;
- __asm __volatile("wr %2,%%g0,%%asi; "
- " ldswa [%1]%%asi,%0; wr %%g0, 0x82, %%asi" :
- "=r" (_lda_v) :
- "r" ((unsigned long)(loc)), "r" (asi));
+ __asm __volatile(
+ "wr %2,%%g0,%%asi; "
+ "ldswa [%1]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi "
+ : "=r" (_lda_v)
+ : "r" ((unsigned long)(loc)), "r" (asi));
return (_lda_v);
}
#else /* __arch64__ */
@@ -585,17 +592,28 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
-" sllx %3,32,%0; wrpr %1,8,%%pstate; or %0,%2,%0; membar #Sync; "
-" lda [%0]%%asi,%0; wrpr %1,0,%%pstate; membar #Sync; "
-" wr %%g0, 0x82, %%asi" : "=&r" (_lda_v), "=&r" (_pstate) :
- "r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi));
+ __asm __volatile(
+ "wr %4,%%g0,%%asi; "
+ "rdpr %%pstate,%1; "
+ "sllx %3,32,%0; "
+ "wrpr %1,8,%%pstate; "
+ "or %0,%2,%0; "
+ "membar #Sync; "
+ "lda [%0]%%asi,%0; "
+ "wrpr %1,0,%%pstate; "
+ "membar #Sync; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lda_v), "=&r" (_pstate)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
} else {
- __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; lda [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
- "r" ((unsigned long)(loc)),
- "r" (_loc_hi), "r" (asi));
+ __asm __volatile(
+ "wr %3,%%g0,%%asi; "
+ "sllx %2,32,%0; "
+ "or %0,%1,%0; "
+ "lda [%0]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lda_v)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
}
return (_lda_v);
}
@@ -608,18 +626,28 @@
_loc_hi = (((u_int64_t)loc)>>32);
if (PHYS_ASI(asi)) {
- __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;"
-" wrpr %1,8,%%pstate; sllx %3,32,%0;"
-" or %0,%2,%0; membar #Sync; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate; "
-" membar #Sync; wr %%g0, 0x82, %%asi" :
- "=&r" (_lda_v), "=&r" (_pstate) :
- "r" ((unsigned long)(loc)), "r" (_loc_hi),
- "r" (asi));
+ __asm __volatile(
+ "wr %4,%%g0,%%asi; "
+ "rdpr %%pstate,%1; "
+ "wrpr %1,8,%%pstate; "
+ "sllx %3,32,%0; "
+ " or %0,%2,%0; "
+ "membar #Sync; "
+ "ldswa [%0]%%asi,%0; "
+ "wrpr %1,0,%%pstate; "
+ "membar #Sync; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lda_v), "=&r" (_pstate)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
} else {
- __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; "
-" or %0,%1,%0; ldswa [%0]%%asi,%0; wr %%g0, 0x82, %%asi" : "=&r" (_lda_v) :
- "r" ((unsigned long)(loc)),
- "r" (_loc_hi), "r" (asi));
+ __asm __volatile(
+ "wr %3,%%g0,%%asi; "
+ "sllx %2,32,%0; "
+ "or %0,%1,%0; "
+ "ldswa [%0]%%asi,%0; "
+ "wr %%g0, 0x82, %%asi "
+ : "=&r" (_lda_v)
+ : "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi));
}
return (_lda_v);
}
Home |
Main Index |
Thread Index |
Old Index