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[src/trunk]: src/sys/arch/mips/mips Hook mips3 cache error vector. No real h...
details: https://anonhg.NetBSD.org/src/rev/ed4a59da9294
branches: trunk
changeset: 500899:ed4a59da9294
user: jeffs <jeffs%NetBSD.org@localhost>
date: Wed Dec 20 05:48:06 2000 +0000
description:
Hook mips3 cache error vector. No real handler, only set-up for a panic.
A real handler is hard.
diffstat:
sys/arch/mips/mips/locore_mips3.S | 44 ++++++++++++++++++++++++++++++++++++++-
sys/arch/mips/mips/mips_machdep.c | 13 +++++++++-
2 files changed, 54 insertions(+), 3 deletions(-)
diffs (113 lines):
diff -r 48c90c04dd2a -r ed4a59da9294 sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Wed Dec 20 05:03:37 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Wed Dec 20 05:48:06 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.61 2000/12/14 21:29:51 jeffs Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.62 2000/12/20 05:48:06 jeffs Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -260,6 +260,20 @@
5: j mips3_SlowFault #1e: no page table present
nop #1f: branch delay slot
VECTOR_END(mips3_XTLBMiss)
+
+/*
+ * Vector to real handler in KSEG1.
+ */
+VECTOR(mips3_cache, unknown)
+ la k0, _C_LABEL(mips3_cacheException)
+ li k1, MIPS_PHYS_MASK
+ and k0, k1
+ li k1, MIPS_KSEG1_START
+ or k0, k1
+ j k0
+ nop
+VECTOR_END(mips3_cache)
+
.set at
@@ -744,6 +758,34 @@
END(mips3_SystemCall)
/*
+ * Panic on cache errors. A lot more could be done to recover
+ * from some types of errors but it is tricky.
+ */
+NESTED_NOPROFILE(mips3_cacheException, KERNFRAME_SIZ, ra)
+ .set noat
+ .mask 0x80000000, -4
+ la k0, panic # return to panic
+ la a0, 9f # panicstr
+ dmfc0 a1, MIPS_COP_0_ERROR_PC
+ mfc0 a2, MIPS_COP_0_CACHE_ERR # 3rd arg cache error
+
+ dmtc0 k0, MIPS_COP_0_ERROR_PC # set return address
+
+ mfc0 k0, MIPS_COP_0_STATUS # restore status
+ li k1, MIPS3_SR_DIAG_PE # ignore further errors
+ or k0, k1
+ mtc0 k0, MIPS_COP_0_STATUS # restore status
+ nop
+ nop
+ nop
+
+ eret
+
+ MSG("cache error @ EPC 0x%x CachErr 0x%x");
+ .set at
+END(mips3_cacheException)
+
+/*
* mips3_KernIntr
*
* Handle an interrupt from kernel mode.
diff -r 48c90c04dd2a -r ed4a59da9294 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Wed Dec 20 05:03:37 2000 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Wed Dec 20 05:48:06 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.108 2000/11/27 06:38:54 soren Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.109 2000/12/20 05:48:06 jeffs Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.108 2000/11/27 06:38:54 soren Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.109 2000/12/20 05:48:06 jeffs Exp $");
#include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h"
@@ -264,6 +264,9 @@
extern char mips3_TLBMiss[], mips3_TLBMissEnd[];
extern char mips3_XTLBMiss[], mips3_XTLBMissEnd[];
+ /* Cache error handler */
+ extern char mips3_cache[], mips3_cacheEnd[];
+
/*
* Copy down exception vector code.
*/
@@ -273,6 +276,9 @@
if (mips3_XTLBMissEnd - mips3_XTLBMiss > 0x80)
panic("startup: XTLB code too large");
+ if (mips3_cacheEnd - mips3_cache > 0x80)
+ panic("startup: Cache error code too large");
+
memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips3_TLBMiss,
mips3_TLBMissEnd - mips3_TLBMiss);
@@ -282,6 +288,9 @@
memcpy((void *)MIPS3_GEN_EXC_VEC, mips3_exception,
mips3_exceptionEnd - mips3_exception);
+ memcpy((void *)MIPS3_CACHE_ERR_EXC_VEC, mips3_cache,
+ mips3_cacheEnd - mips3_cache);
+
/*
* Copy locore-function vector.
*/
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