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[src/trunk]: src/sys/dev/ic Add a whole slew of registers found in the PCnet-...
details: https://anonhg.NetBSD.org/src/rev/1fa9bb8c1189
branches: trunk
changeset: 482627:1fa9bb8c1189
user: thorpej <thorpej%NetBSD.org@localhost>
date: Thu Feb 17 20:18:29 2000 +0000
description:
Add a whole slew of registers found in the PCnet-PCI family.
diffstat:
sys/dev/ic/lancereg.h | 438 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 434 insertions(+), 4 deletions(-)
diffs (truncated from 479 to 300 lines):
diff -r 03e7309e651c -r 1fa9bb8c1189 sys/dev/ic/lancereg.h
--- a/sys/dev/ic/lancereg.h Thu Feb 17 18:42:21 2000 +0000
+++ b/sys/dev/ic/lancereg.h Thu Feb 17 20:18:29 2000 +0000
@@ -1,11 +1,11 @@
-/* $NetBSD: lancereg.h,v 1.2 1998/08/15 10:18:14 mycroft Exp $ */
+/* $NetBSD: lancereg.h,v 1.3 2000/02/17 20:18:29 thorpej Exp $ */
/*-
- * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Charles M. Hannum.
+ * by Charles M. Hannum and Jason R. Thorpe.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -74,6 +74,56 @@
* @(#)if_lereg.h 8.1 (Berkeley) 6/10/93
*/
+/*
+ * Register description for the following Advanced Micro Devices
+ * Ethernet chips:
+ *
+ * - Am7990 Local Area Network Controller for Ethernet (LANCE)
+ * (and its descendent Am79c90 C-LANCE).
+ *
+ * - Am79c900 Integrated Local Area Communications Controller (ILACC)
+ *
+ * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
+ *
+ * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
+ * for ISA
+ *
+ * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
+ * Ethernet Controller for ISA
+ *
+ * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
+ * (for VESA and 486 local busses)
+ *
+ * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
+ * Local Bus
+ *
+ * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
+ * for PCI Local Bus
+ *
+ * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
+ * Ethernet Controller for PCI Local Bus
+ *
+ * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
+ * with OnNow Support
+ *
+ * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
+ * Ethernet Controller with Integrated PHY
+ *
+ * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
+ * Networking Controller.
+ *
+ * Initialization block, transmit descriptor, and receive descriptor
+ * formats are described in two separate files:
+ *
+ * 16-bit software model (LANCE) am7990reg.h
+ *
+ * 32-bit software model (ILACC) am79900reg.h
+ *
+ * Note that the vast majority of the registers described in this file
+ * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
+ * valid on the LANCE.
+ */
+
#define LEBLEN 1536 /* ETHERMTU + header + CRC */
#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */
@@ -83,11 +133,133 @@
#define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr[bix])
#define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr[bix])
-/* register addresses */
+/*
+ * Control and Status Register addresses
+ */
#define LE_CSR0 0x0000 /* Control and status register */
#define LE_CSR1 0x0001 /* low address of init block */
#define LE_CSR2 0x0002 /* high address of init block */
#define LE_CSR3 0x0003 /* Bus master and control */
+#define LE_CSR4 0x0004 /* Test and features control */
+#define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
+#define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
+#define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
+#define LE_CSR8 0x0008 /* Logical Address Filter 0 */
+#define LE_CSR9 0x0009 /* Logical Address Filter 1 */
+#define LE_CSR10 0x000a /* Logical Address Filter 2 */
+#define LE_CSR11 0x000b /* Logical Address Filter 3 */
+#define LE_CSR12 0x000c /* Physical Address 0 */
+#define LE_CSR13 0x000d /* Physical Address 1 */
+#define LE_CSR14 0x000e /* Physical Address 2 */
+#define LE_CSR15 0x000f /* Mode */
+#define LE_CSR16 0x0010 /* Initialization Block addr lower */
+#define LE_CSR17 0x0011 /* Initialization Block addr upper */
+#define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */
+#define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */
+#define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */
+#define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */
+#define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */
+#define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */
+#define LE_CSR24 0x0018 /* Base addr of Rx ring lower */
+#define LE_CSR25 0x0019 /* Base addr of Rx ring upper */
+#define LE_CSR26 0x001a /* Next Rx Desc addr lower */
+#define LE_CSR27 0x001b /* Next Rx Desc addr upper */
+#define LE_CSR28 0x001c /* Current Rx Desc addr lower */
+#define LE_CSR29 0x001d /* Current Rx Desc addr upper */
+#define LE_CSR30 0x001e /* Base addr of Tx ring lower */
+#define LE_CSR31 0x001f /* Base addr of Tx ring upper */
+#define LE_CSR32 0x0020 /* Next Tx Desc addr lower */
+#define LE_CSR33 0x0021 /* Next Tx Desc addr upper */
+#define LE_CSR34 0x0022 /* Current Tx Desc addr lower */
+#define LE_CSR35 0x0023 /* Current Tx Desc addr upper */
+#define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */
+#define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */
+#define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */
+#define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */
+#define LE_CSR40 0x0028 /* Current Rx Byte Count */
+#define LE_CSR41 0x0029 /* Current Rx Status */
+#define LE_CSR42 0x002a /* Current Tx Byte Count */
+#define LE_CSR43 0x002b /* Current Tx Status */
+#define LE_CSR44 0x002c /* Next Rx Byte Count */
+#define LE_CSR45 0x002d /* Next Rx Status */
+#define LE_CSR46 0x002e /* Tx Poll Time Counter */
+#define LE_CSR47 0x002f /* Tx Polling Interval */
+#define LE_CSR48 0x0030 /* Rx Poll Time Counter */
+#define LE_CSR49 0x0031 /* Rx Polling Interval */
+#define LE_CSR58 0x003a /* Software Style */
+#define LE_CSR60 0x003c /* Previous Tx Desc addr lower */
+#define LE_CSR61 0x003d /* Previous Tx Desc addr upper */
+#define LE_CSR62 0x003e /* Previous Tx Byte Count */
+#define LE_CSR63 0x003f /* Previous Tx Status */
+#define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */
+#define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */
+#define LE_CSR66 0x0042 /* Next Tx Byte Count */
+#define LE_CSR67 0x0043 /* Next Tx Status */
+#define LE_CSR72 0x0048 /* Receive Ring Counter */
+#define LE_CSR74 0x004a /* Transmit Ring Counter */
+#define LE_CSR76 0x004c /* Receive Ring Length */
+#define LE_CSR78 0x004e /* Transmit Ring Length */
+#define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO
+ Threshold Control */
+#define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */
+#define LE_CSR84 0x0054 /* DMA addr register lower */
+#define LE_CSR85 0x0055 /* DMA addr register upper */
+#define LE_CSR86 0x0056 /* Buffer Byte Counter */
+#define LE_CSR88 0x0058 /* Chip ID Register lower */
+#define LE_CSR89 0x0059 /* Chip ID Register upper */
+#define LE_CSR92 0x005c /* Ring Length Conversion */
+#define LE_CSR100 0x0064 /* Bus Timeout */
+#define LE_CSR112 0x0070 /* Missed Frame Count */
+#define LE_CSR114 0x0072 /* Receive Collision Count */
+#define LE_CSR116 0x0074 /* OnNow Power Mode Register */
+#define LE_CSR122 0x007a /* Advanced Feature Control */
+#define LE_CSR124 0x007c /* Test Register 1 */
+#define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */
+
+/*
+ * Bus Configuration Register addresses
+ */
+#define LE_BCR0 0x0000 /* Master Mode Read Active */
+#define LE_BCR1 0x0001 /* Master Mode Write Active */
+#define LE_BCR2 0x0002 /* Misc. Configuration */
+#define LE_BCR4 0x0004 /* LED0 Status */
+#define LE_BCR5 0x0005 /* LED1 Status */
+#define LE_BCR6 0x0006 /* LED2 Status */
+#define LE_BCR7 0x0007 /* LED3 Status */
+#define LE_BCR9 0x0009 /* Full-duplex Control */
+#define LE_BCR16 0x0010 /* I/O Base Address lower */
+#define LE_BCR17 0x0011 /* I/O Base Address upper */
+#define LE_BCR18 0x0012 /* Burst and Bus Control Register */
+#define LE_BCR19 0x0013 /* EEPROM Control and Status */
+#define LE_BCR20 0x0014 /* Software Style */
+#define LE_BCR22 0x0016 /* PCI Latency Register */
+#define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */
+#define LE_BCR24 0x0018 /* PCI Subsystem ID */
+#define LE_BCR25 0x0019 /* SRAM Size Register */
+#define LE_BCR26 0x001a /* SRAM Boundary Register */
+#define LE_BCR27 0x001b /* SRAM Interface Control Register */
+#define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */
+#define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */
+#define LE_BCR30 0x001e /* Exp. Bus Data Port */
+#define LE_BCR31 0x001f /* Software Timer Register */
+#define LE_BCR32 0x0020 /* PHY Control and Status Register */
+#define LE_BCR33 0x0021 /* PHY Address Register */
+#define LE_BCR34 0x0022 /* PHY Management Data Register */
+#define LE_BCR35 0x0023 /* PCI Vendor ID Register */
+#define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */
+#define LE_BCR37 0x0025 /* PCI DATA0 Alias */
+#define LE_BCR38 0x0026 /* PCI DATA1 Alias */
+#define LE_BCR39 0x0027 /* PCI DATA2 Alias */
+#define LE_BCR40 0x0028 /* PCI DATA3 Alias */
+#define LE_BCR41 0x0029 /* PCI DATA4 Alias */
+#define LE_BCR42 0x002a /* PCI DATA5 Alias */
+#define LE_BCR43 0x002b /* PCI DATA6 Alias */
+#define LE_BCR44 0x002c /* PCI DATA7 Alias */
+#define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */
+#define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */
+#define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */
+#define LE_BCR48 0x0030 /* LED4 Status */
+#define LE_BCR49 0x0031 /* PHY Select */
/* Control and status register 0 (csr0) */
#define LE_C0_ERR 0x8000 /* error summary */
@@ -112,10 +284,268 @@
\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
/* Control and status register 3 (csr3) */
+#define LE_C3_MISSM 0x1000 /* missed frame mask */
+#define LE_C3_MERRM 0x0800 /* memory error mask */
+#define LE_C3_RINTM 0x0400 /* receive interrupt mask */
+#define LE_C3_TINTM 0x0200 /* transmit interrupt mask */
+#define LE_C3_IDONM 0x0100 /* initialization done mask */
+#define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */
+#define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */
+#define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */
+#define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */
#define LE_C3_BSWP 0x0004 /* byte swap */
#define LE_C3_ACON 0x0002 /* ALE control, eh? */
#define LE_C3_BCON 0x0001 /* byte control */
+/* Control and status register 4 (csr4) */
+#define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
+#define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */
+#define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */
+#define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */
+#define LE_C4_MFCO 0x0200 /* missed frame counter overflow */
+#define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */
+#define LE_C4_UINTCMD 0x0080 /* user interrupt command */
+#define LE_C4_UINT 0x0040 /* user interrupt */
+#define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */
+#define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow
+ mask */
+#define LE_C4_TXSTRT 0x0008 /* transmit start status */
+#define LE_C4_TXSTRTM 0x0004 /* transmit start mask */
+
+/* Control and status register 5 (csr5) */
+#define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */
+#define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */
+#define LE_C5_SINT 0x0800 /* system interrupt */
+#define LE_C5_SINTE 0x0400 /* system interrupt enable */
+#define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */
+#define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */
+#define LE_C5_MPPLBA 0x0020 /* magic packet physical logical
+ broadcast accept */
+#define LE_C5_MPINT 0x0010 /* magic packet interrupt */
+#define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */
+#define LE_C5_MPEN 0x0004 /* magic packet enable */
+#define LE_C5_MPMODE 0x0002 /* magic packet mode */
+#define LE_C5_SPND 0x0001 /* suspend */
+
+/* Control and status register 6 (csr6) */
+#define LE_C6_TLEN 0xf000 /* TLEN from init block */
+#define LE_C6_RLEN 0x0f00 /* RLEN from init block */
+
+/* Control and status register 7 (csr7) */
+#define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */
+#define LE_C7_RDMD 0x2000 /* receive demand */
+#define LE_C7_RDXPOLL 0x1000 /* receive disable polling */
+#define LE_C7_STINT 0x0800 /* software timer interrupt */
+#define LE_C7_STINTE 0x0400 /* software timer interrupt enable */
+#define LE_C7_MREINT 0x0200 /* PHY management read error intr */
+#define LE_C7_MREINTE 0x0100 /* PHY management read error intr
+ enable */
+#define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
+#define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
+ enable */
+#define LE_C7_MCCINT 0x0020 /* PHY management command complete
+ interrupt */
+#define LE_C7_MCCINTE 0x0010 /* PHY management command complete
+ interrupt enable */
+#define LE_C7_MCCIINT 0x0008 /* PHY management command complete
+ internal interrupt */
+#define LE_C7_MCCIINTE 0x0004 /* PHY management command complete
+ internal interrupt enable */
+#define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition
+ interrupt */
+#define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition
+ interrupt enable */
+
+/* control and status register 80 (csr80) */
+#define LE_C80_RCVFW1 0x2000 /* Receive FIFO Watermark 1 */
+#define LE_C80_RCVFW0 0x1000 /* Receive FIFO Watermark 0 */
+ /* 00 16 bytes */
+ /* 01 64 bytes */
+ /* 10 112 bytes */
+ /* 11 reserved */
+#define LE_C80_XMTSP1 0x0800 /* Transmit Start Point 1 */
+#define LE_C80_XMTSP0 0x0400 /* Transmit Start Point 0 */
+ /* 00 0 20 bytes */
+ /* 01 0 64 bytes */
+ /* 10 0 128 bytes */
+ /* 11 0 220 max */
+ /* 00 >0 36 bytes */
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