[src/trunk]: src/sys/arch/sparc/sparc Implement the sun4c hardware-assisted p...

[pk <pk%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/14d72fa63767
branches:  trunk
changeset: 521182:14d72fa63767
user:      pk <pk%NetBSD.org@localhost>
date:      Fri Jan 25 17:40:44 2002 +0000

description:
Implement the sun4c hardware-assisted page flush operation in a separate
function.

diffstat:

 sys/arch/sparc/sparc/cache.c |  37 ++++++++++++++++++++++++++++---------
 sys/arch/sparc/sparc/cache.h |   5 ++++-
 sys/arch/sparc/sparc/cpu.c   |   6 +++++-
 3 files changed, 37 insertions(+), 11 deletions(-)

diffs (97 lines):

diff -r af23a9e2d714 -r 14d72fa63767 sys/arch/sparc/sparc/cache.c
--- a/sys/arch/sparc/sparc/cache.c      Fri Jan 25 17:22:35 2002 +0000
+++ b/sys/arch/sparc/sparc/cache.c      Fri Jan 25 17:40:44 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.59 2001/12/04 00:05:06 darrenr Exp $ */
+/*     $NetBSD: cache.c,v 1.60 2002/01/25 17:40:44 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -430,14 +430,33 @@
 
        cachestats.cs_npgflush++;
        p = (char *)va;
-       if (CACHEINFO.c_hwflush)
-               sta(p, ASI_HWFLUSHPG, 0);
-       else {
-               ls = CACHEINFO.c_linesize;
-               i = NBPG >> CACHEINFO.c_l2linesize;
-               for (; --i >= 0; p += ls)
-                       sta(p, ASI_FLUSHPG, 0);
-       }
+       ls = CACHEINFO.c_linesize;
+       i = NBPG >> CACHEINFO.c_l2linesize;
+       for (; --i >= 0; p += ls)
+               sta(p, ASI_FLUSHPG, 0);
+}
+
+}
+/*
+ * Flush the given virtual page from the cache.
+ * (va is the actual address, and must be aligned on a page boundary.)
+ * This version uses hardware-assisted flush operation and just needs
+ * one write into ASI_HWFLUSHPG space to flush all cache lines.
+ */
+void
+sun4_vcache_flush_page_hw(va)
+       int va;
+{
+       char *p;
+
+#ifdef DEBUG
+       if (va & PGOFSET)
+               panic("cache_flush_page: asked to flush misaligned va 0x%x",va);
+#endif
+
+       cachestats.cs_npgflush++;
+       p = (char *)va;
+       sta(p, ASI_HWFLUSHPG, 0);
 }
 
 /*
diff -r af23a9e2d714 -r 14d72fa63767 sys/arch/sparc/sparc/cache.h
--- a/sys/arch/sparc/sparc/cache.h      Fri Jan 25 17:22:35 2002 +0000
+++ b/sys/arch/sparc/sparc/cache.h      Fri Jan 25 17:40:44 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.h,v 1.24 2001/12/04 00:05:06 darrenr Exp $ */
+/*     $NetBSD: cache.h,v 1.25 2002/01/25 17:40:45 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -76,6 +76,8 @@
  *                     :2;             (unused; must be zero)
  *     };
  *
+ * (The SS2 has 16 MMU contexts, which makes `ct_cid' one bit wider.)
+ *
  * The SPARCstation 1 cache sees virtual addresses as:
  *
  *     struct cache_va {
@@ -166,6 +168,7 @@
 void   sun4_vcache_flush_region __P((int));    /* flush region in cur ctx */
 void   sun4_vcache_flush_segment __P((int, int));/* flush seg in cur ctx */
 void   sun4_vcache_flush_page __P((int va));   /* flush page in cur ctx */
+void   sun4_vcache_flush_page_hw __P((int va));/* flush page in cur ctx */
 void   sun4_cache_flush __P((caddr_t, u_int));/* flush region */
 
 void   srmmu_vcache_flush_context __P((void)); /* flush current context */
diff -r af23a9e2d714 -r 14d72fa63767 sys/arch/sparc/sparc/cpu.c
--- a/sys/arch/sparc/sparc/cpu.c        Fri Jan 25 17:22:35 2002 +0000
+++ b/sys/arch/sparc/sparc/cpu.c        Fri Jan 25 17:40:44 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.125 2001/12/04 00:05:06 darrenr Exp $ */
+/*     $NetBSD: cpu.c,v 1.126 2002/01/25 17:40:45 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -1055,6 +1055,10 @@
                kvm_uncache((caddr_t)trapbase, 1);
                printf(": cache chip bug; trap page uncached");
        }
+
+       /* Use the hardware-assisted page flush routine, if present */
+       if (sc->cacheinfo.c_hwflush)
+               sc->vcache_flush_page = sun4_vcache_flush_page_hw;
 }
 
 #if defined(SUN4M)