[src/trunk]: src/sys/arch/arm/arm * Default dcache_inv_range to xscale_cache_...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/4e28e1023efe
branches:  trunk
changeset: 521195:4e28e1023efe
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Fri Jan 25 21:33:26 2002 +0000

description:
* Default dcache_inv_range to xscale_cache_flushD_rng for XScale
  cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
  xscale_cache_purgeD_rng to work around a bug where a D$
  "invalidate by address" doesn't properly clear the dirty
  bits on the cache block (i80200 errata item #25).

diffstat:

 sys/arch/arm/arm/cpufunc.c |  17 +++++++++++++++--
 1 files changed, 15 insertions(+), 2 deletions(-)

diffs (45 lines):

diff -r 6cd632c58658 -r 4e28e1023efe sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Fri Jan 25 20:57:41 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Fri Jan 25 21:33:26 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.27 2002/01/25 19:19:24 thorpej Exp $     */
+/*     $NetBSD: cpufunc.c,v 1.28 2002/01/25 21:33:26 thorpej Exp $     */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -519,7 +519,7 @@
 
        xscale_cache_purgeD,            /* dcache_wbinv_all     */
        xscale_cache_purgeD_rng,        /* dcache_wbinv_range   */
-/*XXX*/        xscale_cache_purgeD_rng,        /* dcache_inv_range     */
+       xscale_cache_flushD_rng,        /* dcache_inv_range     */
        xscale_cache_cleanD_rng,        /* dcache_wb_range      */
 
        xscale_cache_purgeID,           /* idcache_wbinv_all    */
@@ -703,6 +703,8 @@
 #endif /* CPU_SA110 */
 #ifdef CPU_XSCALE
        if (cputype == CPU_ID_I80200) {
+               int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
+
                i80200_intr_init();
 
                /*
@@ -737,6 +739,17 @@
 
                pte_cache_mode = PT_C;  /* Select write-through cacheing. */
                cpufuncs = xscale_cpufuncs;
+
+               /*
+                * i80200 errata: Step-A0 and A1 have a bug where
+                * D$ dirty bits are not cleared on "invalidate by
+                * address".
+                *
+                * Workaround: Clean cache line before invalidating.
+                */
+               if (rev == 0 || rev == 1)
+                       cpufuncs.cf_dcache_inv_range = xscale_cache_purgeD_rng;
+
                cpu_reset_needs_v4_MMU_disable = 1;     /* XScale needs it */
                get_cachetype();
                return 0;