Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/nathanw_sa]: src/sys/arch/alpha/pci ALCOR/ALCOR2/PYXIS have a 256-byte D...
details: https://anonhg.NetBSD.org/src/rev/5e86047fc8de
branches: nathanw_sa
changeset: 504872:5e86047fc8de
user: thorpej <thorpej%NetBSD.org@localhost>
date: Thu Jul 19 18:42:43 2001 +0000
description:
ALCOR/ALCOR2/PYXIS have a 256-byte DMA prefetch threshold.
diffstat:
sys/arch/alpha/pci/cia_dma.c | 492 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 492 insertions(+), 0 deletions(-)
diffs (truncated from 496 to 300 lines):
diff -r efe1c72fb85d -r 5e86047fc8de sys/arch/alpha/pci/cia_dma.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/alpha/pci/cia_dma.c Thu Jul 19 18:42:43 2001 +0000
@@ -0,0 +1,492 @@
+/* $NetBSD: cia_dma.c,v 1.18.2.2 2001/07/19 18:42:43 thorpej Exp $ */
+
+/*-
+ * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
+
+__KERNEL_RCSID(0, "$NetBSD: cia_dma.c,v 1.18.2.2 2001/07/19 18:42:43 thorpej Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <uvm/uvm_extern.h>
+
+#define _ALPHA_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <alpha/pci/ciareg.h>
+#include <alpha/pci/ciavar.h>
+
+bus_dma_tag_t cia_dma_get_tag __P((bus_dma_tag_t, alpha_bus_t));
+
+int cia_bus_dmamap_create_direct __P((bus_dma_tag_t, bus_size_t, int,
+ bus_size_t, bus_size_t, int, bus_dmamap_t *));
+
+int cia_bus_dmamap_load_sgmap __P((bus_dma_tag_t, bus_dmamap_t, void *,
+ bus_size_t, struct proc *, int));
+
+int cia_bus_dmamap_load_mbuf_sgmap __P((bus_dma_tag_t, bus_dmamap_t,
+ struct mbuf *, int));
+
+int cia_bus_dmamap_load_uio_sgmap __P((bus_dma_tag_t, bus_dmamap_t,
+ struct uio *, int));
+
+int cia_bus_dmamap_load_raw_sgmap __P((bus_dma_tag_t, bus_dmamap_t,
+ bus_dma_segment_t *, int, bus_size_t, int));
+
+void cia_bus_dmamap_unload_sgmap __P((bus_dma_tag_t, bus_dmamap_t));
+
+/*
+ * Direct-mapped window: 1G at 1G
+ */
+#define CIA_DIRECT_MAPPED_BASE (1*1024*1024*1024)
+#define CIA_DIRECT_MAPPED_SIZE (1*1024*1024*1024)
+
+/*
+ * SGMAP window: 8M at 8M
+ */
+#define CIA_SGMAP_MAPPED_BASE (8*1024*1024)
+#define CIA_SGMAP_MAPPED_SIZE (8*1024*1024)
+
+/* ALCOR/ALGOR2/PYXIS have a 256-byte out-bound DMA prefetch threshold. */
+#define CIA_SGMAP_PFTHRESH 256
+
+void cia_tlb_invalidate __P((void));
+void cia_broken_pyxis_tlb_invalidate __P((void));
+
+void (*cia_tlb_invalidate_fn) __P((void));
+
+#define CIA_TLB_INVALIDATE() (*cia_tlb_invalidate_fn)()
+
+struct alpha_sgmap cia_pyxis_bug_sgmap;
+#define CIA_PYXIS_BUG_BASE (128*1024*1024)
+#define CIA_PYXIS_BUG_SIZE (2*1024*1024)
+
+void
+cia_dma_init(ccp)
+ struct cia_config *ccp;
+{
+ bus_addr_t tbase;
+ bus_dma_tag_t t;
+
+ /*
+ * Initialize the DMA tag used for direct-mapped DMA.
+ */
+ t = &ccp->cc_dmat_direct;
+ t->_cookie = ccp;
+ t->_wbase = CIA_DIRECT_MAPPED_BASE;
+ t->_wsize = CIA_DIRECT_MAPPED_SIZE;
+ t->_next_window = NULL;
+ t->_boundary = 0;
+ t->_sgmap = NULL;
+ t->_get_tag = cia_dma_get_tag;
+ t->_dmamap_create = cia_bus_dmamap_create_direct;
+ t->_dmamap_destroy = _bus_dmamap_destroy;
+ t->_dmamap_load = _bus_dmamap_load_direct;
+ t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct;
+ t->_dmamap_load_uio = _bus_dmamap_load_uio_direct;
+ t->_dmamap_load_raw = _bus_dmamap_load_raw_direct;
+ t->_dmamap_unload = _bus_dmamap_unload;
+ t->_dmamap_sync = _bus_dmamap_sync;
+
+ t->_dmamem_alloc = _bus_dmamem_alloc;
+ t->_dmamem_free = _bus_dmamem_free;
+ t->_dmamem_map = _bus_dmamem_map;
+ t->_dmamem_unmap = _bus_dmamem_unmap;
+ t->_dmamem_mmap = _bus_dmamem_mmap;
+
+ /*
+ * Initialize the DMA tag used for sgmap-mapped DMA.
+ */
+ t = &ccp->cc_dmat_sgmap;
+ t->_cookie = ccp;
+ t->_wbase = CIA_SGMAP_MAPPED_BASE;
+ t->_wsize = CIA_SGMAP_MAPPED_SIZE;
+ t->_next_window = NULL;
+ t->_boundary = 0;
+ t->_sgmap = &ccp->cc_sgmap;
+ t->_pfthresh = CIA_SGMAP_PFTHRESH;
+ t->_get_tag = cia_dma_get_tag;
+ t->_dmamap_create = alpha_sgmap_dmamap_create;
+ t->_dmamap_destroy = alpha_sgmap_dmamap_destroy;
+ t->_dmamap_load = cia_bus_dmamap_load_sgmap;
+ t->_dmamap_load_mbuf = cia_bus_dmamap_load_mbuf_sgmap;
+ t->_dmamap_load_uio = cia_bus_dmamap_load_uio_sgmap;
+ t->_dmamap_load_raw = cia_bus_dmamap_load_raw_sgmap;
+ t->_dmamap_unload = cia_bus_dmamap_unload_sgmap;
+ t->_dmamap_sync = _bus_dmamap_sync;
+
+ t->_dmamem_alloc = _bus_dmamem_alloc;
+ t->_dmamem_free = _bus_dmamem_free;
+ t->_dmamem_map = _bus_dmamem_map;
+ t->_dmamem_unmap = _bus_dmamem_unmap;
+ t->_dmamem_mmap = _bus_dmamem_mmap;
+
+ /*
+ * The firmware has set up window 1 as a 1G direct-mapped DMA
+ * window beginning at 1G. We leave it alone. Leave window
+ * 0 alone until we reconfigure it for SGMAP-mapped DMA.
+ * Windows 2 and 3 are already disabled.
+ */
+
+ /*
+ * Initialize the SGMAP. Must align page table to 32k
+ * (hardware bug?).
+ */
+ alpha_sgmap_init(t, &ccp->cc_sgmap, "cia_sgmap",
+ CIA_SGMAP_MAPPED_BASE, 0, CIA_SGMAP_MAPPED_SIZE,
+ sizeof(u_int64_t), NULL, (32*1024));
+
+ /*
+ * Set up window 0 as an 8MB SGMAP-mapped window
+ * starting at 8MB.
+ */
+ REGVAL(CIA_PCI_W0BASE) = CIA_SGMAP_MAPPED_BASE |
+ CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN;
+ alpha_mb();
+
+ REGVAL(CIA_PCI_W0MASK) = CIA_PCI_WnMASK_8M;
+ alpha_mb();
+
+ tbase = ccp->cc_sgmap.aps_ptpa >> CIA_PCI_TnBASE_SHIFT;
+ if ((tbase & CIA_PCI_TnBASE_MASK) != tbase)
+ panic("cia_dma_init: bad page table address");
+ REGVAL(CIA_PCI_T0BASE) = tbase;
+ alpha_mb();
+
+ /*
+ * Pass 1 and 2 (i.e. revision <= 1) of the Pyxis have a
+ * broken scatter/gather TLB; it cannot be invalidated. To
+ * work around this problem, we configure window 2 as an SG
+ * 2M window at 128M, which we use in DMA loopback mode to
+ * read a spill page. This works by causing TLB misses,
+ * causing the old entries to be purged to make room for
+ * the new entries coming in for the spill page.
+ */
+ if ((ccp->cc_flags & CCF_ISPYXIS) != 0 && ccp->cc_rev <= 1) {
+ u_int64_t *page_table;
+ int i;
+
+ cia_tlb_invalidate_fn =
+ cia_broken_pyxis_tlb_invalidate;
+
+ alpha_sgmap_init(t, &cia_pyxis_bug_sgmap,
+ "pyxis_bug_sgmap", CIA_PYXIS_BUG_BASE, 0,
+ CIA_PYXIS_BUG_SIZE, sizeof(u_int64_t), NULL,
+ (32*1024));
+
+ REGVAL(CIA_PCI_W2BASE) = CIA_PYXIS_BUG_BASE |
+ CIA_PCI_WnBASE_SG_EN | CIA_PCI_WnBASE_W_EN;
+ alpha_mb();
+
+ REGVAL(CIA_PCI_W2MASK) = CIA_PCI_WnMASK_2M;
+ alpha_mb();
+
+ tbase = cia_pyxis_bug_sgmap.aps_ptpa >>
+ CIA_PCI_TnBASE_SHIFT;
+ if ((tbase & CIA_PCI_TnBASE_MASK) != tbase)
+ panic("cia_dma_init: bad page table address");
+ REGVAL(CIA_PCI_T2BASE) = tbase;
+ alpha_mb();
+
+ /*
+ * Initialize the page table to point at the spill
+ * page. Leave the last entry invalid.
+ */
+ pci_sgmap_pte64_init_spill_page_pte();
+ for (i = 0, page_table = cia_pyxis_bug_sgmap.aps_pt;
+ i < (CIA_PYXIS_BUG_SIZE / PAGE_SIZE) - 1; i++) {
+ page_table[i] =
+ pci_sgmap_pte64_prefetch_spill_page_pte;
+ }
+ alpha_mb();
+ } else
+ cia_tlb_invalidate_fn = cia_tlb_invalidate;
+
+ CIA_TLB_INVALIDATE();
+
+ /* XXX XXX BEGIN XXX XXX */
+ { /* XXX */
+ extern paddr_t alpha_XXX_dmamap_or; /* XXX */
+ alpha_XXX_dmamap_or = CIA_DIRECT_MAPPED_BASE; /* XXX */
+ } /* XXX */
+ /* XXX XXX END XXX XXX */
+}
+
+/*
+ * Return the bus dma tag to be used for the specified bus type.
+ * INTERNAL USE ONLY!
+ */
+bus_dma_tag_t
+cia_dma_get_tag(t, bustype)
+ bus_dma_tag_t t;
+ alpha_bus_t bustype;
+{
+ struct cia_config *ccp = t->_cookie;
+
+ switch (bustype) {
+ case ALPHA_BUS_PCI:
+ case ALPHA_BUS_EISA:
+ /*
+ * Systems with a CIA can only support 1G
+ * of memory, so we use the direct-mapped window
+ * on busses that have 32-bit DMA.
+ */
+ return (&ccp->cc_dmat_direct);
+
+ case ALPHA_BUS_ISA:
+ /*
+ * ISA doesn't have enough address bits to use
+ * the direct-mapped DMA window, so we must use
+ * SGMAPs.
+ */
+ return (&ccp->cc_dmat_sgmap);
+
+ default:
+ panic("cia_dma_get_tag: shouldn't be here, really...");
+ }
+}
+
+/*
+ * Create a CIA direct-mapped DMA map.
+ */
+int
+cia_bus_dmamap_create_direct(t, size, nsegments, maxsegsz, boundary,
+ flags, dmamp)
+ bus_dma_tag_t t;
Home |
Main Index |
Thread Index |
Old Index