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[src/sommerfeld_i386mp_1]: src/sys/arch/i386 Preliminary support for cloning ...
details: https://anonhg.NetBSD.org/src/rev/424cd664d201
branches: sommerfeld_i386mp_1
changeset: 482303:424cd664d201
user: sommerfeld <sommerfeld%NetBSD.org@localhost>
date: Sat Sep 23 17:30:06 2000 +0000
description:
Preliminary support for cloning MTRR values between CPU's at boot time.
XXX no API to *set* MTRR values yet.
diffstat:
sys/arch/i386/conf/files.i386 | 3 +-
sys/arch/i386/i386/cpu.c | 22 +++-
sys/arch/i386/i386/ipifuncs.c | 4 +-
sys/arch/i386/i386/mtrr.c | 276 +++++++++++++++++++++++++++++++++++++++++
sys/arch/i386/include/cpu.h | 11 +-
sys/arch/i386/include/cpuvar.h | 6 +-
sys/arch/i386/include/intr.h | 5 +-
sys/arch/i386/include/mtrr.h | 52 +++++++
8 files changed, 369 insertions(+), 10 deletions(-)
diffs (truncated from 498 to 300 lines):
diff -r 6c05b7e24866 -r 424cd664d201 sys/arch/i386/conf/files.i386
--- a/sys/arch/i386/conf/files.i386 Sat Sep 23 17:27:00 2000 +0000
+++ b/sys/arch/i386/conf/files.i386 Sat Sep 23 17:30:06 2000 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.i386,v 1.147.2.4 2000/06/25 19:36:57 sommerfeld Exp $
+# $NetBSD: files.i386,v 1.147.2.5 2000/09/23 17:30:06 sommerfeld Exp $
#
# new style config file for i386 architecture
#
@@ -62,6 +62,7 @@
file arch/i386/i386/math_emulate.c math_emulate
file arch/i386/i386/mem.c
file arch/i386/i386/microtime.s
+file arch/i386/i386/mtrr.c
file netns/ns_cksum.c ns
file arch/i386/i386/pmap.c
file arch/i386/i386/process_machdep.c
diff -r 6c05b7e24866 -r 424cd664d201 sys/arch/i386/i386/cpu.c
--- a/sys/arch/i386/i386/cpu.c Sat Sep 23 17:27:00 2000 +0000
+++ b/sys/arch/i386/i386/cpu.c Sat Sep 23 17:30:06 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.1.2.13 2000/08/21 02:36:20 sommerfeld Exp $ */
+/* $NetBSD: cpu.c,v 1.1.2.14 2000/09/23 17:30:06 sommerfeld Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -95,6 +95,7 @@
#include <machine/specialreg.h>
#include <machine/segments.h>
#include <machine/gdt.h>
+#include <machine/mtrr.h>
#if NLAPIC > 0
#include <machine/apicvar.h>
@@ -118,6 +119,8 @@
static struct cpu_info dummy_cpu_info; /* XXX */
struct cpu_info *cpu_info[I386_MAXPROCS] = { &dummy_cpu_info };
+u_int32_t cpus_running = 0;
+
void cpu_hatch __P((void *));
static void cpu_boot_secondary __P((struct cpu_info *ci));
static void cpu_copy_trampoline __P((void));
@@ -297,10 +300,27 @@
if (ci->cpu_class >= CPUCLASS_486)
lcr0(rcr0() | CR0_WP);
#endif
+#if defined(I686_CPU)
+ /*
+ * On a P6 or above, enable global TLB caching if the
+ * hardware supports it.
+ */
if (cpu_feature & CPUID_PGE)
lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */
+ /*
+ * On a P6 or above, initialize MTRR's if the hardware supports them.
+ */
+ if (cpu_feature & CPUID_MTRR) {
+ if ((ci->ci_flags & CPUF_AP) == 0)
+ mtrr_init_first();
+ mtrr_init_cpu(ci);
+ }
+#endif
+#ifdef MULTIPROCESSOR
ci->ci_flags |= CPUF_RUNNING;
+ cpus_running |= 1 << cpu_number();
+#endif
}
diff -r 6c05b7e24866 -r 424cd664d201 sys/arch/i386/i386/ipifuncs.c
--- a/sys/arch/i386/i386/ipifuncs.c Sat Sep 23 17:27:00 2000 +0000
+++ b/sys/arch/i386/i386/ipifuncs.c Sat Sep 23 17:30:06 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ipifuncs.c,v 1.1.2.6 2000/08/21 00:27:00 sommerfeld Exp $ */
+/* $NetBSD: ipifuncs.c,v 1.1.2.7 2000/09/23 17:30:06 sommerfeld Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -58,6 +58,7 @@
#include <machine/atomic.h>
#include <machine/cpuvar.h>
#include <machine/i82093var.h>
+#include <machine/mtrr.h>
#include <ddb/db_output.h>
@@ -79,6 +80,7 @@
0,
#endif
pmap_do_tlb_shootdown,
+ mtrr_reload_cpu,
};
void
diff -r 6c05b7e24866 -r 424cd664d201 sys/arch/i386/i386/mtrr.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/i386/i386/mtrr.c Sat Sep 23 17:30:06 2000 +0000
@@ -0,0 +1,276 @@
+/* $NetBSD: mtrr.c,v 1.1.2.1 2000/09/23 17:30:06 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "opt_multiprocessor.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/lock.h>
+#include <sys/user.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/specialreg.h>
+#include <machine/atomic.h>
+#include <machine/cpuvar.h>
+#include <machine/cpufunc.h>
+#include <machine/mtrr.h>
+
+static void i686_mtrr_reload(int);
+
+struct mtrr_state
+{
+ uint32_t msraddr;
+ uint64_t msrval;
+};
+
+static struct mtrr_state
+mtrr[] = {
+ { MSR_MTRRphysBase0 },
+ { MSR_MTRRphysMask0 },
+ { MSR_MTRRphysBase1 },
+ { MSR_MTRRphysMask1 },
+ { MSR_MTRRphysBase2 },
+ { MSR_MTRRphysMask2 },
+ { MSR_MTRRphysBase3 },
+ { MSR_MTRRphysMask3 },
+ { MSR_MTRRphysBase4 },
+ { MSR_MTRRphysMask4 },
+ { MSR_MTRRphysBase5 },
+ { MSR_MTRRphysMask5 },
+ { MSR_MTRRphysBase6 },
+ { MSR_MTRRphysMask6 },
+ { MSR_MTRRphysBase7 },
+ { MSR_MTRRphysMask7 },
+ { MSR_MTRRfix64K_00000 },
+ { MSR_MTRRfix16K_80000 },
+ { MSR_MTRRfix16K_A0000 },
+ { MSR_MTRRfix4K_C0000 },
+ { MSR_MTRRfix4K_C8000 },
+ { MSR_MTRRfix4K_D0000 },
+ { MSR_MTRRfix4K_D8000 },
+ { MSR_MTRRfix4K_E0000 },
+ { MSR_MTRRfix4K_E8000 },
+ { MSR_MTRRfix4K_F0000 },
+ { MSR_MTRRfix4K_F8000 },
+ { MSR_MTRRdefType }
+};
+
+static const int nmtrr = sizeof(mtrr)/sizeof(mtrr[0]);
+
+#ifdef MULTIPROCESSOR
+static volatile uint32_t mtrr_waiting;
+#endif
+
+void
+mtrr_dump(const char *tag)
+{
+ int i;
+
+ for (i=0; i<nmtrr; i++)
+ printf("%s: %x: %016llx\n",
+ tag, mtrr[i].msraddr, rdmsr(mtrr[i].msraddr));
+}
+
+/*
+ * The Intel Archicture Software Developer's Manual volume 3 (systems
+ * programming) section 9.12.8 describes a simple 15-step process for
+ * updating the MTRR's on all processors on a multiprocessor system.
+ * If synch is nonzero, assume we're being called from an IPI handler,
+ * and synchronize with all running processors.
+ */
+
+/*
+ * 1. Broadcast to all processor to execute the following code sequence.
+ */
+
+static void
+i686_mtrr_reload(int synch)
+{
+ int i;
+ uint32_t cr0, cr3, cr4;
+ uint32_t origcr0, origcr4;
+#ifdef MULTIPROCESSOR
+ uint32_t mymask = 1 << cpu_number();
+#endif
+
+ /*
+ * 2. Disable interrupts
+ */
+
+ disable_intr();
+
+#ifdef MULTIPROCESSOR
+ if (synch) {
+ /*
+ * 3. Wait for all processors to reach this point.
+ */
+
+ i386_atomic_setbits_l(&mtrr_waiting, mymask);
+
+ while (mtrr_waiting != cpus_running)
+ DELAY(10);
+ }
+#endif
+
+ /*
+ * 4. Enter the no-fill cache mode (set the CD flag in CR0 to 1 and
+ * the NW flag to 0)
+ */
+
+ origcr0 = cr0 = rcr0();
+ cr0 |= CR0_CD;
+ cr0 &= ~CR0_NW;
+ lcr0(cr0);
+
+ /*
+ * 5. Flush all caches using the WBINVD instruction.
+ */
+
+ wbinvd();
+
+ /*
+ * 6. Clear the PGE flag in control register CR4 (if set).
+ */
+
+ origcr4 = cr4 = rcr4();
+ cr4 &= ~CR4_PGE;
+ lcr4(cr4);
+
+ /*
+ * 7. Flush all TLBs (execute a MOV from control register CR3
+ * to another register and then a move from that register back
+ * to CR3)
+ */
+
+ cr3 = rcr3();
+ lcr3(cr3);
+
+ /*
+ * 8. Disable all range registers (by clearing the E flag in
+ * register MTRRdefType. If only variable ranges are being
+ * modified, software may clear the valid bits for the
+ * affected register pairs instead.
+ */
+ /* disable MTRRs (E = 0) */
+ wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800); /* XXX MAGIC */
+
+ /*
+ * 9. Update the MTRR's
+ */
+
+ for (i=0; i<nmtrr; i++) {
+ uint64_t val = mtrr[i].msrval;
+ uint32_t addr = mtrr[i].msraddr;
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