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[src/nathanw_sa]: src/sys/arch/arm/sa11x0 Initial copy of SA11x0 support from...
details: https://anonhg.NetBSD.org/src/rev/f3f8d30831d8
branches: nathanw_sa
changeset: 504824:f3f8d30831d8
user: rjs <rjs%NetBSD.org@localhost>
date: Sun Jul 08 23:37:54 2001 +0000
description:
Initial copy of SA11x0 support from hpcarm.
diffstat:
sys/arch/arm/sa11x0/sa11x0_comreg.h | 97 +++++++++++
sys/arch/arm/sa11x0/sa11x0_comvar.h | 97 +++++++++++
sys/arch/arm/sa11x0/sa11x0_dmacreg.h | 95 +++++++++++
sys/arch/arm/sa11x0/sa11x0_io_asm.S | 288 +++++++++++++++++++++++++++++++++++
sys/arch/arm/sa11x0/sa11x0_ostreg.h | 80 +++++++++
sys/arch/arm/sa11x0/sa11x0_sspreg.h | 76 +++++++++
sys/arch/arm/sa11x0/sa11x1_pcicreg.h | 80 +++++++++
sys/arch/arm/sa11x0/sa11xx_pcicreg.h | 44 +++++
8 files changed, 857 insertions(+), 0 deletions(-)
diffs (truncated from 889 to 300 lines):
diff -r 6c07d918aa60 -r f3f8d30831d8 sys/arch/arm/sa11x0/sa11x0_comreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sa11x0/sa11x0_comreg.h Sun Jul 08 23:37:54 2001 +0000
@@ -0,0 +1,97 @@
+/* $NetBSD: sa11x0_comreg.h,v 1.1.8.2 2001/07/08 23:37:54 rjs Exp $ */
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/* SA11[01]0 integrated UART interface */
+
+/* #define SACOM_BASE 0x80050000 */
+
+#define SACOM_FREQ (3686400 / 16)
+#define SACOMSPEED(b) (SACOM_FREQ / (b) - 1)
+
+/* size of I/O space */
+#define SACOM_NPORTS 9
+
+#define SACOM_TXFIFOLEN 8
+#define SACOM_RXFIFOLEN 12
+
+/* UART control register 0 */
+#define SACOM_CR0 0x00
+#define CR0_PE 0x01 /* Parity enable */
+#define CR0_OES 0x02 /* Odd/even parity select */
+#define CR0_SBS 0x04 /* Stop bit select */
+#define CR0_DSS 0x08 /* Data size select */
+#define CR0_SCE 0x10 /* Sample clock enable */
+#define CR0_RCE 0x20 /* Receive clock edge enable */
+#define CR0_TCE 0x40 /* Transmit clock edge enable */
+
+/* UART control register 1 and 2 - baud rate divisor */
+#define SACOM_CR1 0x04
+#define SACOM_CR2 0x08
+
+/* UART control register 3 */
+#define SACOM_CR3 0x0C
+#define CR3_RXE 0x01 /* Receiver enable */
+#define CR3_TXE 0x02 /* Transmitter enable */
+#define CR3_BRK 0x04 /* Break */
+#define CR3_RIE 0x08 /* Receive FIFO interrupt enable */
+#define CR3_TIE 0x10 /* Transmit FIFO interrupt enable */
+#define CR3_LBM 0x20 /* Loopback mode */
+
+/* UART data register */
+#define SACOM_DR 0x14
+#define DR_PRE 0x100 /* Parity error */
+#define DR_FRE 0x200 /* Framing error */
+#define DR_ROR 0x400 /* Receiver overrun */
+
+/* UART status register 0 */
+#define SACOM_SR0 0x1C
+#define SR0_TFS 0x01 /* Transmit FIFO service request */
+#define SR0_RFS 0x02 /* Receive FIFO service request */
+#define SR0_RID 0x04 /* Receiver idle */
+#define SR0_RBB 0x08 /* Receiver begin of break */
+#define SR0_REB 0x10 /* Receiver end of break */
+#define SR0_EIF 0x20 /* Error in FIFO */
+
+/* UART status register 1 */
+#define SACOM_SR1 0x20
+#define SR1_TBY 0x01 /* Transmitter busy */
+#define SR1_RNE 0x02 /* Receive FIFO not empty */
+#define SR1_TNF 0x04 /* Transmit FIFO not full */
+#define SR1_PRE 0x08 /* Parity error */
+#define SR1_FRE 0x10 /* Framing error */
+#define SR1_ROR 0x20 /* Receive FIFO overrun */
diff -r 6c07d918aa60 -r f3f8d30831d8 sys/arch/arm/sa11x0/sa11x0_comvar.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sa11x0/sa11x0_comvar.h Sun Jul 08 23:37:54 2001 +0000
@@ -0,0 +1,97 @@
+/* $NetBSD: sa11x0_comvar.h,v 1.1.8.2 2001/07/08 23:37:54 rjs Exp $ */
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef _ARM_SA11X0_COMVAR_H_
+#define _ARM_SA11X0_COMVAR_H_
+
+/* Hardware flag masks */
+#define COM_HW_NOIEN 0x01
+#define COM_HW_DEV_OK 0x20
+#define COM_HW_CONSOLE 0x40
+#define COM_HW_KGDB 0x80
+
+#define RX_TTY_BLOCKED 0x01
+#define RX_TTY_OVERFLOWED 0x02
+#define RX_IBUF_BLOCKED 0x04
+#define RX_IBUF_OVERFLOWED 0x08
+#define RX_ANY_BLOCK 0x0f
+
+#define SACOM_RING_SIZE 2048
+
+struct sacom_softc {
+ struct device sc_dev;
+ bus_addr_t sc_baseaddr;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+#ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
+ void *sc_si;
+#endif
+ struct tty *sc_tty;
+
+
+ u_char *sc_rbuf, *sc_ebuf;
+
+ u_char *sc_tba;
+ u_int sc_tbc, sc_heldtbc;
+
+ u_char *volatile sc_rbget,
+ *volatile sc_rbput;
+ volatile u_int sc_rbavail;
+
+ /* status flags */
+ int sc_hwflags, sc_swflags;
+
+ volatile u_int sc_rx_flags,
+ sc_tx_busy,
+ sc_tx_done,
+ sc_tx_stopped,
+ sc_st_check,
+ sc_rx_ready;
+ volatile int sc_heldchange;
+
+ /* control registers */
+ u_int sc_cr0, sc_cr3;
+ u_int sc_speed;
+
+ /* power management hooks */
+ int (*enable)(struct sacom_softc *);
+ int (*disable)(struct sacom_softc *);
+
+ int enabled;
+};
+
+#endif /* _ARM_SA11X0_COMVAR_H_ */
diff -r 6c07d918aa60 -r f3f8d30831d8 sys/arch/arm/sa11x0/sa11x0_dmacreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sa11x0/sa11x0_dmacreg.h Sun Jul 08 23:37:54 2001 +0000
@@ -0,0 +1,95 @@
+/* $NetBSD: sa11x0_dmacreg.h,v 1.1.8.2 2001/07/08 23:37:54 rjs Exp $ */
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+/* SA11[01]0 integrated DMA controller */
+
+#define SADMAC_NPORTS 40
+
+#define SADMAC_DAR0 0x00 /* DMA device address register */
+#define SADMAC_DCR0_SET 0x04 /* DMA control/status (set) */
+#define SADMAC_DCR0_CLR 0x08 /* DMA control/status (clear) */
+#define SADMAC_DCR0 0x0C /* DMA control/status (read only) */
+#define SADMAC_DBSA0 0x10 /* DMA Buffer A start address */
+#define SADMAC_DBTA0 0x14 /* DMA Buffer A transfer count */
+#define SADMAC_DBSB0 0x18 /* DMA Buffer B start address */
+#define SADMAC_DBTB0 0x1C /* DMA Buffer B transfer count */
+
+#define SADMAC_DAR1 0x20
+#define SADMAC_DCR1_SET 0x24
+#define SADMAC_DCR1_CLR 0x28
+#define SADMAC_DCR1 0x2C
+#define SADMAC_DBSA1 0x30
+#define SADMAC_DBTA1 0x34
+#define SADMAC_DBSB1 0x38
+#define SADMAC_DBTB1 0x3C
+
+#define SADMAC_DAR2 0x40
+#define SADMAC_DCR2_SET 0x44
+#define SADMAC_DCR2_CLR 0x48
+#define SADMAC_DCR2 0x4C
+#define SADMAC_DBSA2 0x50
+#define SADMAC_DBTA2 0x54
+#define SADMAC_DBSB2 0x58
+#define SADMAC_DBTB2 0x5C
+
+#define SADMAC_DAR3 0x60
+#define SADMAC_DCR3_SET 0x64
+#define SADMAC_DCR3_CLR 0x68
+#define SADMAC_DCR3 0x6C
+#define SADMAC_DBSA3 0x70
+#define SADMAC_DBTA3 0x74
+#define SADMAC_DBSB3 0x78
+#define SADMAC_DBTB3 0x7C
+
+#define SADMAC_DAR4 0x80
+#define SADMAC_DCR4_SET 0x84
+#define SADMAC_DCR4_CLR 0x88
+#define SADMAC_DCR4 0x8C
+#define SADMAC_DBSA4 0x90
+#define SADMAC_DBTA4 0x94
+#define SADMAC_DBSB4 0x98
+#define SADMAC_DBTB4 0x9C
+
+#define SADMAC_DAR5 0xA0
+#define SADMAC_DCR5_SET 0xA4
+#define SADMAC_DCR5_CLR 0xA8
+#define SADMAC_DCR5 0xAC
+#define SADMAC_DBSA5 0xB0
+#define SADMAC_DBTA5 0xB4
+#define SADMAC_DBSB5 0xB8
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