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[src/sommerfeld_i386mp_1]: src/sys/arch/i386 "Merge" in revised cache probing...
details: https://anonhg.NetBSD.org/src/rev/c523e515f339
branches: sommerfeld_i386mp_1
changeset: 482390:c523e515f339
user: sommerfeld <sommerfeld%NetBSD.org@localhost>
date: Mon May 07 16:51:46 2001 +0000
description:
"Merge" in revised cache probing code (including amd cache size
probing). Separate feature probing from output formatting, and call
uvm_recolor() at an appropriate moment.
diffstat:
sys/arch/i386/i386/cpu.c | 41 ++-
sys/arch/i386/i386/machdep.c | 643 ++++++++++++++++++++++++++++++++----------
sys/arch/i386/include/cpu.h | 28 +-
3 files changed, 548 insertions(+), 164 deletions(-)
diffs (truncated from 1041 to 300 lines):
diff -r 089ba692518b -r c523e515f339 sys/arch/i386/i386/cpu.c
--- a/sys/arch/i386/i386/cpu.c Fri May 04 20:19:57 2001 +0000
+++ b/sys/arch/i386/i386/cpu.c Mon May 07 16:51:46 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.1.2.19 2001/01/10 04:38:32 sommerfeld Exp $ */
+/* $NetBSD: cpu.c,v 1.1.2.20 2001/05/07 16:51:46 sommerfeld Exp $ */
/*-
* Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -175,6 +175,42 @@
return 0;
}
+static void
+cpu_vm_init(struct cpu_info *ci)
+{
+ int ncolors = 2, i;
+
+ for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
+ struct i386_cache_info *cai;
+ int tcolors;
+
+ cai = &ci->ci_cinfo[i];
+
+ tcolors = atop(cai->cai_totalsize);
+ switch(cai->cai_associativity) {
+ case ~0:
+ tcolors = 1;
+ break;
+ case 0:
+ case 1:
+ break;
+ default:
+ tcolors /= cai->cai_associativity;
+ }
+ ncolors = max(ncolors, tcolors);
+ }
+
+ /*
+ * Knowing the size of the largest cache on this CPU, re-color
+ * our pages.
+ */
+ if (ncolors <= uvmexp.ncolors)
+ return;
+ printf("%s: %d page colors\n", ci->ci_dev->dv_xname, ncolors);
+ uvm_page_recolor(ncolors);
+}
+
+
void
cpu_attach(parent, self, aux)
struct device *parent, *self;
@@ -296,6 +332,9 @@
default:
panic("unknown processor type??\n");
}
+ cpu_vm_init(ci);
+
+
#if defined(MULTIPROCESSOR)
if (mp_verbose) {
diff -r 089ba692518b -r c523e515f339 sys/arch/i386/i386/machdep.c
--- a/sys/arch/i386/i386/machdep.c Fri May 04 20:19:57 2001 +0000
+++ b/sys/arch/i386/i386/machdep.c Mon May 07 16:51:46 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.376.2.20 2001/04/30 16:23:11 sommerfeld Exp $ */
+/* $NetBSD: machdep.c,v 1.376.2.21 2001/05/07 16:51:46 sommerfeld Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2000 The NetBSD Foundation, Inc.
@@ -229,65 +229,47 @@
void add_mem_cluster __P((u_int64_t, u_int64_t, u_int32_t));
#endif /* !defnied(REALBASEMEM) && !defined(REALEXTMEM) */
-const struct i386_cache_info *cpu_itlb_info, *cpu_dtlb_info, *cpu_icache_info,
- *cpu_dcache_info, *cpu_l2cache_info;
-
-const struct i386_cache_info {
- size_t cai_offset;
- u_int8_t cai_desc;
- const char *cai_string;
- u_int cai_totalsize;
- u_int cai_linesize;
-} i386_cache_info[] = {
- { offsetof(struct cpu_info, ci_itlb_info),
- 0x01, "4K: 32 entries 4-way", 32, 4 * 1024 },
- { offsetof(struct cpu_info, ci_itlb2_info),
- 0x02, "4M: 2 entries", 2, 4 * 1024 * 1024 },
- { offsetof(struct cpu_info, ci_dtlb_info),
- 0x03, "4K: 64 entries 4-way", 64, 4 * 1024 },
- { offsetof(struct cpu_info, ci_dtlb2_info),
- 0x04, "4M: 8 entries 4-way", 8, 4 * 1024 * 1024 },
- { offsetof(struct cpu_info, ci_icache_info),
- 0x06, "8K 32b/line 4-way", 8 * 1024, 32 },
- { offsetof(struct cpu_info, ci_icache_info),
- 0x08, "16K 32b/line 4-way", 16 * 1024, 32 },
- { offsetof(struct cpu_info, ci_dcache_info),
- 0x0a, "8K 32b/line 2-way", 8 * 1024, 32 },
- { offsetof(struct cpu_info, ci_dcache_info),
- 0x0c, "16K 32b/line 2/4-way", 16 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x40, "not present", 0, 0 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x41, "128K 32b/line 4-way", 128 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x42, "256K 32b/line 4-way", 256 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x43, "512K 32b/line 4-way", 512 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x44, "1M 32b/line 4-way", 1 * 1024 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x45, "2M 32b/line 4-way", 2 * 1024 * 1024, 32 },
- { offsetof(struct cpu_info, ci_itlb_info),
- 0x50, "4K/4M: 64 entries", 64, 4 * 1024 },
- { offsetof(struct cpu_info, ci_dtlb_info),
- 0x5b, "4K/4M: 64 entries", 64, 4 * 1024 },
- { offsetof(struct cpu_info, ci_dcache_info),
- 0x66, "8K 64b/line 4-way", 8 * 1024, 64 },
- { offsetof(struct cpu_info, ci_icache_info),
- 0x70, "12K uOp cache 4-way", 12 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x7a, "256K 64b/line 8-way", 256 * 1024, 64 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x82, "256K 32b/line 8-way", 256 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x84, "1M 32b/line 8-way", 1 * 1024 * 1024, 32 },
- { offsetof(struct cpu_info, ci_l2cache_info),
- 0x85, "2M 32b/line 8-way", 2 * 1024 * 1024, 32 },
- { 0,
- 0, NULL, 0, 0 },
+const struct i386_cache_info
+intel_cpuid_cache_info[] = {
+ { CAI_ITLB, 0x01, 32, 4 * 1024, 4 },
+ { CAI_ITLB2, 0x02, 2, 4 * 1024 * 1024, ~0 },
+ { CAI_DTLB, 0x03, 64, 4 * 1024, 4 },
+ { CAI_DTLB2, 0x04, 8, 4 * 1024 * 1024, 4 },
+ { CAI_ICACHE, 0x06, 8 * 1024, 32, 4 },
+ { CAI_ICACHE, 0x08, 16 * 1024, 32, 4 },
+ { CAI_DCACHE, 0x0a, 8 * 1024, 32, 2 },
+ { CAI_DCACHE, 0x0c, 16 * 1024, 32, 4 },
+ { CAI_L2CACHE, 0x40, 0, 0, 0, "not present" },
+ { CAI_L2CACHE, 0x41, 128 * 1024, 32, 4 },
+ { CAI_L2CACHE, 0x42, 256 * 1024, 32, 4 },
+ { CAI_L2CACHE, 0x43, 512 * 1024, 32, 4 },
+ { CAI_L2CACHE, 0x44, 1024 * 1024, 32, 4 },
+ { CAI_L2CACHE, 0x45, 2 * 1024 * 1024, 32, 4 },
+ { CAI_ITLB, 0x50, 64, 4 * 1024, ~0, "4K/4M: 64 entries" },
+ { CAI_ITLB, 0x51, 64, 4 * 1024, ~0, "4K/4M: 128 entries" },
+ { CAI_ITLB, 0x52, 64, 4 * 1024, ~0, "4K/4M: 256 entries" },
+ { CAI_DTLB, 0x5b, 64, 4 * 1024, ~0, "4K/4M: 64 entries" },
+ { CAI_DTLB, 0x5c, 64, 4 * 1024, ~0, "4K/4M: 128 entries" },
+ { CAI_DTLB, 0x5d, 64, 4 * 1024, ~0, "4K/4M: 256 entries" },
+ { CAI_DCACHE, 0x66, 8 * 1024, 64, 4 },
+ { CAI_DCACHE, 0x67, 16 * 1024, 64, 4 },
+ { CAI_DCACHE, 0x68, 32 * 1024, 64, 4 },
+ { CAI_ICACHE, 0x70, 12 * 1024, 32, 8, "12K uOp cache 8-way"},
+ { CAI_ICACHE, 0x71, 16 * 1024, 32, 8, "16K uOp cache 8-way"},
+ { CAI_ICACHE, 0x72, 32 * 1024, 32, 8, "32K uOp cache 8-way"},
+ { CAI_L2CACHE, 0x79, 128 * 1024, 64, 8 },
+ { CAI_L2CACHE, 0x7a, 256 * 1024, 64, 8 },
+ { CAI_L2CACHE, 0x7b, 512 * 1024, 64, 8 },
+ { CAI_L2CACHE, 0x7c, 1024 * 1024, 64, 8 },
+
+ { CAI_L2CACHE, 0x82, 256 * 1024, 32, 8 },
+ { CAI_L2CACHE, 0x84, 1 * 1024 * 1024, 32, 8 },
+ { CAI_L2CACHE, 0x85, 2 * 1024 * 1024, 32, 8 },
+ { 0, 0, 0, 0, 0, NULL },
};
-static const struct i386_cache_info *i386_cache_info_lookup __P((u_int8_t));
+static const struct i386_cache_info *
+cache_info_lookup(const struct i386_cache_info *cai, u_int8_t desc);
/*
* Map Brand ID from cpuid instruction to brand name.
@@ -308,6 +290,9 @@
void cyrix6x86_cpu_setup __P((struct cpu_info *));
void winchip_cpu_setup __P((struct cpu_info *));
+void amd_family5_setup __P((struct cpu_info *));
+
+static void amd_cpuid_cpu_cacheinfo __P((struct cpu_info *));
static __inline u_char
cyrix_read_reg(u_char reg)
@@ -323,20 +308,101 @@
outb(0x23, data);
}
+static char *
+print_cache_config(struct cpu_info *ci, int cache_tag, char *name, char *sep)
+{
+ char cbuf[7];
+ struct i386_cache_info *cai = &ci->ci_cinfo[cache_tag];
+
+ if (cai->cai_totalsize == 0)
+ return sep;
+
+ if (sep == NULL)
+ printf("%s: ", ci->ci_dev->dv_xname);
+ else
+ printf("%s", sep);
+ if (name != NULL)
+ printf("%s ", name);
+
+ if (cai->cai_string != NULL) {
+ printf("%s", cai->cai_string);
+ } else {
+ format_bytes(cbuf, sizeof(cbuf), cai->cai_totalsize);
+ printf("%s %db/line ", cbuf, cai->cai_linesize);
+ }
+ switch (cai->cai_associativity) {
+ case 0:
+ printf("disabled");
+ break;
+ case 1:
+ printf("direct-mapped");
+ break;
+ case ~0:
+ printf("fully associative");
+ /* XXX Don't need any color bins? */
+ break;
+ default:
+ printf("%d-way", cai->cai_associativity);
+ break;
+ }
+ return ", ";
+}
+
+static char *
+print_tlb_config(struct cpu_info *ci, int cache_tag, char *name, char *sep)
+{
+ char cbuf[7];
+ struct i386_cache_info *cai = &ci->ci_cinfo[cache_tag];
+
+ if (cai->cai_totalsize == 0)
+ return sep;
+
+ if (sep == NULL)
+ printf("%s: ", ci->ci_dev->dv_xname);
+ else
+ printf("%s", sep);
+ if (name != NULL)
+ printf("%s ", name);
+
+ if (cai->cai_string != NULL) {
+ printf("%s", cai->cai_string);
+ } else {
+ format_bytes(cbuf, sizeof(cbuf), cai->cai_linesize);
+ printf("%d %s entries ", cai->cai_totalsize, cbuf);
+ switch (cai->cai_associativity) {
+ case 0:
+ printf("disabled");
+ break;
+ case 1:
+ printf("direct-mapped");
+ break;
+ case ~0:
+ printf("fully associative");
+ break;
+ default:
+ printf("%d-way", cai->cai_associativity);
+ break;
+ }
+ }
+ return ", ";
+}
+
/*
* Machine-dependent startup code
*/
void
cpu_startup()
{
+#if 0
+ struct cpu_info *ci = curcpu();
+#endif
caddr_t v;
int sz, x;
vaddr_t minaddr, maxaddr;
vsize_t size;
char pbuf[9];
-#if NBIOSCALL > 0
- extern int biostramp_image_size;
- extern u_char biostramp_image[];
+#if 0
+ int bigcache, cachesize;
#endif
/*
@@ -429,26 +495,6 @@
format_bytes(pbuf, sizeof(pbuf), bufpages * PAGE_SIZE);
printf("using %d buffers containing %s of memory\n", nbuf, pbuf);
-#if NBIOSCALL > 0
- /*
- * this should be caught at kernel build time, but put it here
- * in case someone tries to fake it out...
- */
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