[src/trunk]: src/sys/arch/mips/mips Cast the various uses of cache_noop to th...

[he <he%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/40247d40e01c
branches:  trunk
changeset: 581688:40247d40e01c
user:      he <he%NetBSD.org@localhost>
date:      Fri Jun 03 20:48:28 2005 +0000

description:
Cast the various uses of cache_noop to the proper function pointer
type of the target instead of (void*).  Appeases -Wcast-qual.

diffstat:

 sys/arch/mips/mips/cache.c |  52 ++++++++++++++++++++++++++-------------------
 1 files changed, 30 insertions(+), 22 deletions(-)

diffs (98 lines):

diff -r 2d788e5cd907 -r 40247d40e01c sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Fri Jun 03 20:42:56 2005 +0000
+++ b/sys/arch/mips/mips/cache.c        Fri Jun 03 20:48:28 2005 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.27 2005/03/26 09:51:02 tsutsui Exp $       */
+/*     $NetBSD: cache.c,v 1.28 2005/06/03 20:48:28 he Exp $    */
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.27 2005/03/26 09:51:02 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.28 2005/06/03 20:48:28 he Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -1073,9 +1073,11 @@
                break;
 #ifdef MIPS_DISABLE_L1_CACHE
        case 0:
-               mips_cache_ops.mco_icache_sync_all = (void *)cache_noop;
-               mips_cache_ops.mco_icache_sync_range = (void *)cache_noop;
-               mips_cache_ops.mco_icache_sync_range_index = (void *)cache_noop;
+               mips_cache_ops.mco_icache_sync_all = cache_noop;
+               mips_cache_ops.mco_icache_sync_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
+               mips_cache_ops.mco_icache_sync_range_index =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
                break;
 #endif
        default:
@@ -1116,17 +1118,20 @@
                break;
 #ifdef MIPS_DISABLE_L1_CACHE
        case 0:
-               mips_cache_ops.mco_pdcache_wbinv_all = (void *)cache_noop;
-               mips_cache_ops.mco_intern_pdcache_wbinv_all =
-                   (void *)cache_noop;
-               mips_cache_ops.mco_pdcache_wbinv_range = (void *)cache_noop;
+               mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
+               mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop;
+               mips_cache_ops.mco_pdcache_wbinv_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
                mips_cache_ops.mco_pdcache_wbinv_range_index =
-                   (void *)cache_noop;
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
                mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
-                   (void *)cache_noop;
-               mips_cache_ops.mco_pdcache_inv_range = (void *)cache_noop;
-               mips_cache_ops.mco_pdcache_wb_range = (void *)cache_noop;
-               mips_cache_ops.mco_intern_pdcache_wb_range = (void *)cache_noop;
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
+               mips_cache_ops.mco_pdcache_inv_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
+               mips_cache_ops.mco_pdcache_wb_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
+               mips_cache_ops.mco_intern_pdcache_wb_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
                break;
 #endif
        default:
@@ -1141,23 +1146,26 @@
 #ifdef CACHE_DEBUG
                printf("  Dcache is coherent\n");
 #endif
-               mips_cache_ops.mco_pdcache_wbinv_all = (void *)cache_noop;
-               mips_cache_ops.mco_pdcache_wbinv_range = (void *)cache_noop;
+               mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
+               mips_cache_ops.mco_pdcache_wbinv_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
                mips_cache_ops.mco_pdcache_wbinv_range_index =
-                   (void *)cache_noop;
-               mips_cache_ops.mco_pdcache_inv_range = (void *)cache_noop;
-               mips_cache_ops.mco_pdcache_wb_range = (void *)cache_noop;
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
+               mips_cache_ops.mco_pdcache_inv_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
+               mips_cache_ops.mco_pdcache_wb_range =
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
        }
        if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
 #ifdef CACHE_DEBUG
                printf("  Icache is coherent against Dcache\n");
 #endif
                mips_cache_ops.mco_intern_pdcache_wbinv_all =
-                   (void *)cache_noop;
+                   cache_noop;
                mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
-                   (void *)cache_noop;
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
                mips_cache_ops.mco_intern_pdcache_wb_range =
-                   (void *)cache_noop;
+                   (void (*)(vaddr_t, vsize_t))cache_noop;
        }
 }
 #endif /* MIPS32 || MIPS64 */