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[src/trunk]: src/sys/arch/arm Split all the model/version-specific cpufuncs i...
details: https://anonhg.NetBSD.org/src/rev/5957c09cf476
branches: trunk
changeset: 517343:5957c09cf476
user: thorpej <thorpej%NetBSD.org@localhost>
date: Sat Nov 10 23:14:08 2001 +0000
description:
Split all the model/version-specific cpufuncs into separate files
corresponding to the model/version.
diffstat:
sys/arch/arm/arm/cpufunc_asm.S | 1154 +------------------------------
sys/arch/arm/arm/cpufunc_asm_arm3.S | 60 +
sys/arch/arm/arm/cpufunc_asm_arm67.S | 110 ++
sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S | 99 ++
sys/arch/arm/arm/cpufunc_asm_arm8.S | 285 +++++++
sys/arch/arm/arm/cpufunc_asm_arm9.S | 139 +++
sys/arch/arm/arm/cpufunc_asm_armv4.S | 66 +
sys/arch/arm/arm/cpufunc_asm_sa1.S | 383 ++++++++++
sys/arch/arm/arm/cpufunc_asm_xscale.S | 321 ++++++++
sys/arch/arm/conf/files.arm | 11 +-
10 files changed, 1478 insertions(+), 1150 deletions(-)
diffs (truncated from 2705 to 300 lines):
diff -r 8ee0ebd9e895 -r 5957c09cf476 sys/arch/arm/arm/cpufunc_asm.S
--- a/sys/arch/arm/arm/cpufunc_asm.S Sat Nov 10 23:12:41 2001 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm.S Sat Nov 10 23:14:08 2001 +0000
@@ -1,11 +1,6 @@
-/* $NetBSD: cpufunc_asm.S,v 1.10 2001/10/18 14:10:07 rearnsha Exp $ */
+/* $NetBSD: cpufunc_asm.S,v 1.11 2001/11/10 23:14:08 thorpej Exp $ */
/*
- * xscale support code Copyright (c) 2001 Matt Thomas
- * arm7tdmi support code Copyright (c) 2001 John Fremlin
- * arm8 support code Copyright (c) 1997 ARM Limited
- * arm8 support code Copyright (c) 1997 Causality Limited
- * arm9 support code Copyright (C) 2001 ARM Limited
* Copyright (c) 1997,1998 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
@@ -49,10 +44,6 @@
#include <machine/cpu.h>
#include <machine/asm.h>
-sp .req r13
-lr .req r14
-pc .req r15
-
.text
.align 0
@@ -97,9 +88,11 @@
* All other registers are CPU architecture specific
*/
-/*ENTRY(cpufunc_control)
+#if 0 /* See below. */
+ENTRY(cpufunc_control)
mcr p15, 0, r0, c1, c0, 0
- mov pc, lr*/
+ mov pc, lr
+#endif
ENTRY(cpufunc_domains)
mcr p15, 0, r0, c3, c0, 0
@@ -125,1143 +118,6 @@
mov r0, r3 /* Return old value */
mov pc, lr
-#ifdef CPU_ARM3
- /* The ARM3 has its control register in a different place. */
-ENTRY(arm3_control)
- mrc p15, 0, r3, c2, c0, 0 /* Read the control register */
- bic r2, r3, r0 /* Clear bits */
- eor r2, r2, r1 /* XOR bits */
-
- teq r2, r3 /* Only write if there is a change */
- mcrne p15, 0, r2, c2, c0, 0 /* Write new control register */
- mov r0, r3 /* Return old value */
- mov pc, lr
-#endif
-
-#ifdef CPU_ARM8
-ENTRY(arm8_clock_config)
- mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */
- bic r2, r3, #0x11 /* turn off dynamic clocking
- and clear L bit */
- mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
-
- bic r2, r3, r0 /* Clear bits */
- eor r2, r2, r1 /* XOR bits */
- bic r2, r2, #0x10 /* clear the L bit */
-
- bic r1, r2, #0x01 /* still keep dynamic clocking off */
- mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
- mov r0, r0 /* NOP */
- mov r0, r0 /* NOP */
- mov r0, r0 /* NOP */
- mov r0, r0 /* NOP */
- mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
- mov r0, r3 /* Return old value */
- mov pc, lr
-#endif /* CPU_ARM8 */
-
-/*
- * Functions to set the MMU Translation Table Base register
- */
-
-#if defined(CPU_ARM6) || defined(CPU_ARM7)
-ENTRY(arm67_setttb)
-
- /*
- * We need to flush the cache as it uses virtual addresses that
- * are about to change
- */
- mcr p15, 0, r0, c7, c0, 0
-
- /* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0
-
- /* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c5, c0, 0
-
- /* For good measure we will flush the IDC as well */
- mcr p15, 0, r0, c7, c0, 0
-
- /* Make sure that pipeline is emptied */
- mov r0, r0
- mov r0, r0
-
- mov pc, lr
-#endif /* CPU_ARM6 || CPU_ARM7 */
-
-#ifdef CPU_ARM7TDMI
-
-ENTRY(arm7tdmi_setttb)
- mov r1,r0 /* store the ttb in a safe place */
- mov r2,lr /* ditto with lr */
-
- bl _C_LABEL(arm7tdmi_cache_flushID)
-
- /* Write the TTB */
- mcr p15, 0, r1, c2, c0, 0
-
- /* If we have updated the TTB we must flush the TLB */
- bl _C_LABEL(arm7tdmi_tlb_flushID)
- /* For good measure we will flush the IDC as well */
- bl _C_LABEL(arm7tdmi_cache_flushID)
-
- mov pc, r2
-#endif /* CPU_7TDMI */
-
-#ifdef CPU_ARM8
-ENTRY(arm8_setttb)
- /* We need to clean and flush the cache as it uses virtual
- * addresses that are about to change
- */
- mrs r3, cpsr_all
- orr r1, r3, #(I32_bit | F32_bit)
- msr cpsr_all , r1
-
- stmfd sp!, {r0-r3, lr}
- bl _C_LABEL(arm8_cache_cleanID)
- ldmfd sp!, {r0-r3, lr}
- mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
-
- /* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0
-
- /* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0
-
- /* For good measure we will flush the IDC as well */
- mcr p15, 0, r0, c7, c7, 0
-
- /* Make sure that pipeline is emptied */
- mov r0, r0
- mov r0, r0
- msr cpsr_all , r3
-
- mov pc, lr
-#endif /* CPU_ARM8 */
-
-#ifdef CPU_ARM9
-ENTRY(arm9_setttb)
- /*
- * Since we use the caches in write-through mode, we only have to
- * drain the write buffers and flush the caches.
- */
- mcr p15, 0, r0, c7, c7, 0 /* Flush I+D Caches */
- mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
-
- mcr p15, 0, r0, c2, c0, 0 /* Load new ttb */
-
- mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
- mov pc, lr
-#endif /* CPU_ARM9 */
-
-#if defined(CPU_SA110) || defined(CPU_XSCALE)
-Lblock_userspace_access:
- .word _C_LABEL(block_userspace_access)
-#endif
-
-#if defined(CPU_SA110)
-ENTRY(sa110_setttb)
- /* We need to flush the cache as it uses virtual addresses that are about to change */
-#ifdef CACHE_CLEAN_BLOCK_INTR
- mrs r3, cpsr_all
- orr r1, r3, #(I32_bit | F32_bit)
- msr cpsr_all , r1
-#else
- ldr r3, Lblock_userspace_access
- ldr r2, [r3]
- orr r1, r2, #1
- str r1, [r3]
-#endif
- stmfd sp!, {r0-r3, lr}
- bl _C_LABEL(sa110_cache_cleanID)
- ldmfd sp!, {r0-r3, lr}
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
- mcr p15, 0, r0, c7, c10, 4 /* drain write (& fill) buffer */
-
- /* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0 /* set translation table base */
-
- /* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I&D TLB */
-
- /* The cleanID above means we only need to flush the I cache here */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
-
- /* Make sure that pipeline is emptied */
- mov r0, r0
- mov r0, r0
-#ifdef CACHE_CLEAN_BLOCK_INTR
- msr cpsr_all, r3
-#else
- str r2, [r3]
-#endif
- mov pc, lr
-#endif /* CPU_SA110 */
-
-#if defined(CPU_XSCALE)
-ENTRY(xscale_setttb)
- /* We need to flush the cache as it uses virtual addresses that are about to change */
-#ifdef CACHE_CLEAN_BLOCK_INTR
- mrs r3, cpsr_all
- orr r1, r3, #(I32_bit | F32_bit)
- msr cpsr_all , r1
-#else
- ldr r3, Lblock_userspace_access
- ldr r2, [r3]
- orr r1, r2, #1
- str r1, [r3]
-#endif
- stmfd sp!, {r0-r3, lr}
- bl _C_LABEL(xscale_cache_cleanID)
- ldmfd sp!, {r0-r3, lr}
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
- mcr p15, 0, r0, c7, c10, 4 /* drain write (& fill) buffer */
-
- /* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0 /* set translation table base */
-
- /* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I&D TLB */
-
- /* The cleanID above means we only need to flush the I cache here */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache & BTB */
-
- /* Make sure that pipeline is emptied */
- mrc p15, 0, r0, c2, c0, 0 /* read some register in CP15 */
- mov r0, r0 /* for the read to complete */
- sub pc, pc, #4 /* branch to next instruction */
- /* (flush the instruction pipeline) */
-#ifdef CACHE_CLEAN_BLOCK_INTR
- msr cpsr_all, r3
-#else
- str r2, [r3]
-#endif
- mov pc, lr
-#endif /* CPU_XSCALE */
-
-/*
- * TLB functions
- */
-
-#if defined(CPU_ARM6) || defined(CPU_ARM7)
-ENTRY(arm67_tlb_flush)
- mcr p15, 0, r0, c5, c0, 0
- mov pc, lr
-
-ENTRY(arm67_tlb_purge)
- mcr p15, 0, r0, c6, c0, 0
- mov pc, lr
-#endif /* CPU_ARM6 || CPU_ARM7 */
-
-#ifdef CPU_ARM7TDMI
-ENTRY(arm7tdmi_tlb_flushID)
- mov r0,#0
- mcr p15, 0, r0, c8, c7, 0
- mov pc,lr
-
-ENTRY(arm7tdmi_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c7, 1
- mov pc,lr
-#endif
-#ifdef CPU_ARM8
-ENTRY(arm8_tlb_flushID)
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
- mov pc, lr
-
-ENTRY(arm8_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
- mov pc, lr
-#endif /* CPU_ARM8 */
-
-#if defined (CPU_ARM9) || defined(CPU_SA110) || defined(CPU_XSCALE)
-ENTRY(armv4_tlb_flushID)
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
- mov pc, lr
-
-#if defined(CPU_SA110)
-ENTRY(sa110_tlb_flushID_SE)
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