Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/x68k/dev Disable array chain mode by default, since...
details: https://anonhg.NetBSD.org/src/rev/d486c15d04ee
branches: trunk
changeset: 509352:d486c15d04ee
user: minoura <minoura%NetBSD.org@localhost>
date: Wed May 02 12:48:24 2001 +0000
description:
Disable array chain mode by default, since it is unused by any of
the current devices.
Add more flexibility in the API.
diffstat:
sys/arch/x68k/dev/dmacvar.h | 19 ++-
sys/arch/x68k/dev/intio_dmac.c | 243 ++++++++++++++++++++++++++++++++--------
2 files changed, 209 insertions(+), 53 deletions(-)
diffs (truncated from 480 to 300 lines):
diff -r ecc04d991a60 -r d486c15d04ee sys/arch/x68k/dev/dmacvar.h
--- a/sys/arch/x68k/dev/dmacvar.h Wed May 02 12:18:45 2001 +0000
+++ b/sys/arch/x68k/dev/dmacvar.h Wed May 02 12:48:24 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dmacvar.h,v 1.3 2001/04/30 05:47:31 minoura Exp $ */
+/* $NetBSD: dmacvar.h,v 1.4 2001/05/02 12:48:24 minoura Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -58,10 +58,12 @@
int dx_ocr; /* direction */
int dx_scr; /* SCR value */
void *dx_device; /* (initial) device address */
- bus_dma_segment_t dx_seg; /* b_d_s_t for the array chain */
+#ifdef DMAC_ARRAYCHAIN
struct dmac_sg_array *dx_array; /* DMAC array chain */
- int dx_arraysize; /* size of above */
int dx_done;
+#endif
+ int dx_nextoff; /* for continued operation */
+ int dx_nextsize;
};
/*
@@ -112,10 +114,17 @@
/* ch, name, normalv, normal, errorv, error */
int dmac_free_channel __P((struct device*, int, void*));
/* ch, channel */
+struct dmac_dma_xfer *dmac_alloc_xfer __P((struct dmac_channel_stat*,
+ bus_dma_tag_t, bus_dmamap_t));
+int dmac_load_xfer __P((struct device*, struct dmac_dma_xfer *));
+
+int dmac_start_xfer __P((struct device*, struct dmac_dma_xfer*));
+int dmac_start_xfer_offset __P((struct device*, struct dmac_dma_xfer*,
+ u_int, u_int));
+int dmac_abort_xfer __P((struct device*, struct dmac_dma_xfer*));
+/* Compatibility function: alloc, fill defaults, load */
struct dmac_dma_xfer *dmac_prepare_xfer __P((struct dmac_channel_stat*,
bus_dma_tag_t,
bus_dmamap_t,
int, int, void*));
/* chan, dmat, map, dir, sequence, dar */
-#define dmac_finish_xfer(xfer) free(xfer, M_DEVBUF)
-int dmac_start_xfer __P((struct device*, struct dmac_dma_xfer*));
diff -r ecc04d991a60 -r d486c15d04ee sys/arch/x68k/dev/intio_dmac.c
--- a/sys/arch/x68k/dev/intio_dmac.c Wed May 02 12:18:45 2001 +0000
+++ b/sys/arch/x68k/dev/intio_dmac.c Wed May 02 12:48:24 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intio_dmac.c,v 1.8 2001/04/30 05:47:31 minoura Exp $ */
+/* $NetBSD: intio_dmac.c,v 1.9 2001/05/02 12:48:24 minoura Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -45,8 +45,6 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
-#include <sys/malloc.h>
-#include <sys/extent.h>
#include <uvm/uvm_extern.h>
#include <machine/bus.h>
@@ -66,7 +64,10 @@
#endif
static void dmac_init_channels __P((struct dmac_softc*));
-static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*));
+#ifdef DMAC_ARRAYCHAIN
+static int dmac_program_arraychain __P((struct device*, struct dmac_dma_xfer*,
+ u_int, u_int));
+#endif
static int dmac_done __P((void*));
static int dmac_error __P((void*));
@@ -149,6 +150,9 @@
DMAC_CHAN_SIZE*i, DMAC_CHAN_SIZE,
&sc->sc_channels[i].ch_bht);
sc->sc_channels[i].ch_xfer.dx_dmamap = 0;
+ /* reset the status register */
+ bus_space_write_1(sc->sc_bst, sc->sc_channels[i].ch_bht,
+ DMAC_REG_CSR, 0xff);
}
return;
@@ -175,7 +179,8 @@
char intrname[16];
int r, dummy;
- DPRINTF (3, ("dmac_alloc_channel, %d, %s\n", ch, name));
+ printf ("%s: allocating ch %d for %s.\n",
+ sc->sc_dev.dv_xname, ch, name);
DPRINTF (3, ("dmamap=%p\n", (void*) chan->ch_xfer.dx_dmamap));
#ifdef DIAGNOSTIC
if (ch < 0 || ch >= DMAC_NCHAN)
@@ -186,6 +191,7 @@
panic ("DMAC: wrong user name.");
#endif
+#ifdef DMAC_ARRAYCHAIN
/* allocate the DMAC arraychaining map */
r = bus_dmamem_alloc(intio->sc_dmat,
sizeof(struct dmac_sg_array) * DMAC_MAPSIZE,
@@ -200,12 +206,13 @@
BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
if (r)
panic ("DMAC: cannot map DMA safe memory");
+#endif
- /* fill the channel status structure. */
+ /* fill the channel status structure by the default values. */
strcpy(chan->ch_name, name);
chan->ch_dcr = (DMAC_DCR_XRM_CSWH | DMAC_DCR_OTYP_EASYNC |
DMAC_DCR_OPS_8BIT);
- chan->ch_ocr = (DMAC_OCR_SIZE_BYTE_NOPACK | DMAC_OCR_REQG_EXTERNAL);
+ chan->ch_ocr = (DMAC_OCR_SIZE_BYTE | DMAC_OCR_REQG_EXTERNAL);
chan->ch_normalv = normalv;
chan->ch_errorv = errorv;
chan->ch_normal = normal;
@@ -253,7 +260,8 @@
int ch;
void *channel;
{
- struct dmac_softc *sc = (void*) self;
+ struct intio_softc *intio = (void*) self;
+ struct dmac_softc *sc = (void*) intio->sc_dmac;
struct dmac_channel_stat *chan = &sc->sc_channels[ch];
DPRINTF (3, ("dmac_free_channel, %d\n", ch));
@@ -263,6 +271,11 @@
if (ch != chan->ch_channel)
return -1;
+#ifdef DMAC_ARRAYCHAIN
+ bus_dmamem_unmap(intio->sc_dmat, (caddr_t) chan->ch_map,
+ sizeof(struct dmac_sg_array) * DMAC_MAPSIZE);
+ bus_dmamem_free(intio->sc_dmat, &chan->ch_seg[0], 1);
+#endif
chan->ch_name[0] = 0;
intio_intr_disestablish(chan->ch_normalv, channel);
intio_intr_disestablish(chan->ch_errorv, channel);
@@ -274,6 +287,55 @@
* Initialization / deinitialization per transfer.
*/
struct dmac_dma_xfer *
+dmac_alloc_xfer (chan, dmat, dmamap)
+ struct dmac_channel_stat *chan;
+ bus_dma_tag_t dmat;
+ bus_dmamap_t dmamap;
+{
+ struct dmac_dma_xfer *xf = &chan->ch_xfer;
+ struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc;
+
+ DPRINTF (3, ("dmac_alloc_xfer\n"));
+ xf->dx_channel = chan;
+ xf->dx_dmamap = dmamap;
+ xf->dx_tag = dmat;
+#ifdef DMAC_ARRAYCHAIN
+ xf->dx_array = chan->ch_map;
+ xf->dx_done = 0;
+#endif
+ return xf;
+}
+
+int
+dmac_load_xfer (self, xf)
+ struct device *self;
+ struct dmac_dma_xfer *xf;
+{
+ struct dmac_softc *sc = (void*) self;
+ struct dmac_channel_stat *chan = xf->dx_channel;
+
+ DPRINTF (3, ("dmac_load_xfer\n"));
+
+ xf->dx_ocr &= ~DMAC_OCR_CHAIN_MASK;
+ if (xf->dx_dmamap->dm_nsegs == 1)
+ xf->dx_ocr |= DMAC_OCR_CHAIN_DISABLED;
+ else {
+ xf->dx_ocr |= DMAC_OCR_CHAIN_ARRAY;
+ xf->dx_nextoff = ~0;
+ xf->dx_nextsize = ~0;
+ }
+
+ bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
+ bus_space_write_1(sc->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr);
+ bus_space_write_1(sc->sc_bst, chan->ch_bht,
+ DMAC_REG_OCR, (xf->dx_ocr | chan->ch_ocr));
+ bus_space_write_4(sc->sc_bst, chan->ch_bht,
+ DMAC_REG_DAR, (int) xf->dx_device);
+
+ return 0;
+}
+
+struct dmac_dma_xfer *
dmac_prepare_xfer (chan, dmat, dmamap, dir, scr, dar)
struct dmac_channel_stat *chan;
bus_dma_tag_t dmat;
@@ -281,17 +343,16 @@
int dir, scr;
void *dar;
{
- struct dmac_dma_xfer *xf = &chan->ch_xfer;
+ struct dmac_dma_xfer *xf;
+ struct dmac_softc *sc = (struct dmac_softc*) chan->ch_softc;
- DPRINTF (3, ("dmac_prepare_xfer\n"));
- xf->dx_channel = chan;
- xf->dx_dmamap = dmamap;
- xf->dx_tag = dmat;
+ xf = dmac_alloc_xfer(chan, dmat, dmamap);
+
xf->dx_ocr = dir & DMAC_OCR_DIR_MASK;
xf->dx_scr = scr & (DMAC_SCR_MAC_MASK|DMAC_SCR_DAC_MASK);
xf->dx_device = dar;
- xf->dx_array = chan->ch_map;
- xf->dx_done = 0;
+
+ dmac_load_xfer(&sc->sc_dev, xf);
return xf;
}
@@ -314,44 +375,87 @@
struct device *self;
struct dmac_dma_xfer *xf;
{
+ return dmac_start_xfer_offset(self, xf, 0, 0);
+}
+
+int
+dmac_start_xfer_offset(self, xf, offset, size)
+ struct device *self;
+ struct dmac_dma_xfer *xf;
+ u_int offset;
+ u_int size;
+{
struct dmac_softc *sc = (void*) self;
struct dmac_channel_stat *chan = xf->dx_channel;
- int c;
+ struct x68k_bus_dmamap *dmamap = xf->dx_dmamap;
+ int c, go = DMAC_CCR_STR|DMAC_CCR_INT;
DPRINTF (3, ("dmac_start_xfer\n"));
#ifdef DMAC_DEBUG
debugchan=chan;
#endif
+ if (size == 0) {
+#ifdef DIAGNOSTIC
+ if (offset != 0)
+ panic ("dmac_start_xfer_offset: invalid offset %x",
+ offset);
+#endif
+ size = dmamap->dm_mapsize;
+ }
+
+#ifdef DMAC_ARRAYCHAIN
+#ifdef DIAGNOSTIC
+ if (xf->dx_done)
+ panic("dmac_start_xfer: DMA transfer in progress");
+#endif
+#endif
DPRINTF (3, ("First program:\n"));
+#ifdef DIAGNOSTIC
+ if ((offset >= dmamap->dm_mapsize) ||
+ (offset + size > dmamap->dm_mapsize))
+ panic ("dmac_start_xfer_offset: invalid offset: "
+ "offset=%d, size=%d, mapsize=%d",
+ offset, size, dmamap->dm_mapsize);
+#endif
/* program DMAC in single block mode or array chainning mode */
- if (xf->dx_dmamap->dm_nsegs == 1) {
+ if (dmamap->dm_nsegs == 1) {
DPRINTF(3, ("single block mode\n"));
- bus_space_write_4(sc->sc_bst, chan->ch_bht,
- DMAC_REG_MAR,
- (int) xf->dx_dmamap->dm_segs[0].ds_addr);
- bus_space_write_2(sc->sc_bst, chan->ch_bht,
- DMAC_REG_MTCR,
- (int) xf->dx_dmamap->dm_segs[0].ds_len);
+#ifdef DIAGNOSTIC
+ if (dmamap->dm_mapsize != dmamap->dm_segs[0].ds_len)
+ panic ("dmac_start_xfer_offset: dmamap curruption");
+#endif
+ if (offset == xf->dx_nextoff &&
+ size == xf->dx_nextsize) {
+ /* Use continued operation */
+ go |= DMAC_CCR_CNT;
+ xf->dx_nextoff += size;
+ } else {
+ bus_space_write_4(sc->sc_bst, chan->ch_bht,
+ DMAC_REG_MAR,
+ (int) dmamap->dm_segs[0].ds_addr
+ + offset);
+ bus_space_write_2(sc->sc_bst, chan->ch_bht,
+ DMAC_REG_MTCR, (int) size);
+ xf->dx_nextoff = offset;
+ xf->dx_nextsize = size;
+ }
+#ifdef DMAC_ARRAYCHAIN
xf->dx_done = 1;
+#endif
Home |
Main Index |
Thread Index |
Old Index